LNBH25 datasheet(22/34 Pages) STMICROELECTRONICS

22 / 34 page

I²C interface protocol

LNBH25

22/34

Doc ID 022433 Rev 4

N/A = Reserved bit.

All bits reset to 0 at power-on.

7.4

Status registers

The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic

functions described in the following tables.

N/A = Reserved bit.

All bits reset to 0 at power-on.

BIT

Name

Value

Description

Bit 6

THERM

If Thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and

LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master

after the overtemperature condition is removed (OTF=0).

In case of Thermal protection activation (OTF=1) the LNB output (VOUT pin) is

automatically enabled as soon as the overtemperature condition is removed

(OTF=0) with the previous VSEL bits setting.

Bit 7

(MSB)

COMP

DC-DC converter compensation set to use HIGH ESR capacitors (VUP pin)

DC-DC converter compensation set to use LOW ESR capacitors (VUP pin)

Table 10.

DATA 4 (Read/Write register. Register address = 0X5) (continued)

Table 11.

STATUS 1 (Read register. Register address = 0X0)

BIT

Name

Value

Description

Bit 0

(LSB)

OLF

VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 9 for

the overload operation settings (ISET, PCL, TIMER bits).

No overload protection has been triggered to the VOUT pin (IOUT < IMAX).

Bit 1

N/A

Reserved

Bit 2

VMON

Output voltage (VOUT pin) lower than VMON specification thresholds. Refer to

Table 17.

Output voltage (VOUT pin) is within the VMON specifications.

Bit 3

N/A

Reserved

Bit 4

PDO

Overcurrent detected on output pull-down stage for a time longer than the deglitch

period. This may happen due to an external voltage source present on the LNB

output (VOUT pin).

No overcurrent detected on output pull-down stage.

Bit 5

N/A

Reserved

Bit 6

OTF

Junction overtemperature is detected, TJ > 150 °C. See also THERM bit setting in

Table 10.

Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal

protection threshold.

Bit 7

(MSB)

PNG

Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 13.

Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 13.

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