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L6751CTR датащи(PDF) 20 Page - STMicroelectronics

номер детали L6751CTR
подробное описание детали  Digitally controlled dual PWM for Intel VR12 and AMD SVI
PDF  57 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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L6751CTR датащи(HTML) 20 Page - STMicroelectronics

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Device configuration and pin-strapping tables
L6751C
20/57
DocID025037 Rev 1
4.2
Programming Hi-Z level
The L6751C is able to manage different levels for Hi-Z on PWMx guaranteeing flexibility in
driving different external drivers as well as DrMOS ICs.
After EN assertion and before soft-start, the device uses PWM1 and PWM2 to detect the
driver/DrMOS connected in order to program the suitable Hi-Z level of PWMx signals. During
regulation, the Hi-Z level is used to force the external MOSFETs in high impedance state.
PWM1 sources a constant 10
A current, if its voltage results higher than 2.8 V,
Hi-Z
level used during the regulation is 1.4 V, if lower, PWM2 information is used.
PWM2 is kept in Hi-Z, if its voltage results higher than 2 V, Hi-Z level used during
the regulation is 2 V, if lower, 1.6 V.
An external resistor divider can be placed on PWM1 and PWM2 to force the detection of the
correct Hi-Z level. They must be designed considering the external driver/DrMOS selected
and the Hi-Z level requested.
Table 6. Device configuration
SVI address
DROOP (see Table 8)
IMAX / SIMAX
BOOT / TMAX
DPM
VR12
0000b
Enabled.
See Table 8
SeeTable 10
Supported
VR12(1) ()
0010b
0100b
MPhase: as per Table 9.
SPhase: disabled
AMD
n/a
MPhase: enabled. SPhase:
as per Table 9.
Ignored
TMAX(2)
supported
1. In DDR mode, single-phase reference is multi-phase VOUT/2 (JMode disabled).
2. Refer to Table 10 and choose any of the resistor combinations leading to the desired TNMAX. Other settings are ignored.
Table 7. Phase number programming
PHASE #
PWM1 to PWM3
PWM4
PWM5
PWM6
3
To driver
1 k
 to VCC5
4
To driver
1 k
 to VCC5
5
To driver
1 k
 to VCC5
6
To driver



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