TABLE 1. Glossary of Terms (Continued)

Active Scan Chain

The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given

moment. When a ’PSC110F is selected with all of its LSPs parked, the active scan chain is the

current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDI

B

→ the current ’PSC110F register → the local scan ring registers → a PAD bit → TDO

Table 4 for Unparked configurations of the LSP network.

Level 1 Protocol

Level 1 is the protocol used to address a ’PSC110F.

Level 2 Protocol

Level 2 is the protocol that is used once a ’PSC110F is selected. Level 2 protocol is IEEE Std.

1149.1 compliant when an individual ’PSC110F is selected.

PAD

A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit

eliminates the prop delay that would be added by the ’PSC110F LSPN logic between TDI

TDO

thus allowing data to be scanned at higher frequencies without violating set-up and hold times.

LSB

Least Significant Bit, the right-most position in a register (bit 0)

MSB

Most Significant Bit, the left-most position in a register

TABLE 2. Detailed Pin Description Table

Pin #

Name

I/O (Note 1)

(SOIC

Description

& LCC)

TMS

B

TTL Input w/Pull-Up

Resistor

10

BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP

Controller of the SCANPSC110F Bridge. Also controls sequencing of the TAPs

which are on the three (3) local scan chains.

TDI

B

TTL Input w/Pull-Up

Resistor

12

BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the

’PSC110F through this input pin.

TDO

B

TRI-STATEable,

13

BACKPLANE TEST DATA OUTPUT: This output drives test data from the

’PSC110F and the local TAPs, back toward the scan master controller.

32 mA/64 mA Drive,

Reduced-Swing,

Output

TCK

B

TTL Schmitt Trigger

Input

11

TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock

signal that controls all scan operations of the ’PSC110F and of the three (3)

local scan ports.

TRST

TTL Input w/Pull-Up

9

TEST RESET: An asynchronous reset signal (active low) which initializes the

’PSC110F logic.

Resistor

S

(0–5)

TTL Inputs

2, 3, 4,

SLOT IDENTIFICATION: The configuration of these six (6) pins is used to

identify (assign a unique address to) each ’PSC110F on the system backplane.

5, 6, 7

OE

TTL Input

1

OUTPUT ENABLE for the Local Scan Ports, active low. When high, this

active-low control signal TRI-STATEs all three local scan ports on the

’PSC110F, to enable an alternate resource to access one or more of the three

(3) local scan chains.

TDO

L(1–3)

TRI-STATEable,

15,19,

TEST DATA OUTPUTS: Individual output for each of the three (3) local scan

ports.

24 mA/24 mA

24

Drive Outputs

TDI

L(1–3)

TTL Inputs w/Pull-Up

18, 23,

TEST DATA INPUTS: Individual scan data input for each of the three (3) local

scan ports.

Resistors

27

TMS

L(1–3)

TRI-STATEable,

16, 20,

TEST MODE SELECT OUTPUTS: Individual output for each of the three (3)

local scan ports. TMS

to be present on a connected TMS input, per the IEEE 1149.1 requirement)

24 mA/24 mA

25

Drive Outputs

TCK

L(1–3)

TRI-STATEable,

17, 22,

LOCAL TEST CLOCK OUTPUTS: Individual output for each of the three (3)

local scan ports. These are buffered versions of TCK

24 mA/24 mA

26

Drive Output

V

CC

Power Supply Voltage

8, 28

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