TMS416409A, TMS417409A, TMS426409A, TMS427409A

4194304 BY 4-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES

SMKS893B – AUGUST 1996 – REVISED APRIL 1997

21

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

Address

W

OE

DQ1 – DQ4

tRWC

Row

Column

Don’t Care

Don’t Care

Don’t Care

Data

Out

Don’t Care

Don’t Care

Data

In

tRAS

tRCD

tT

tCAS

tRP

tCRP

tCP

tT

tCAH

tASC

tRAH

tASR

tRAD

tRCS

tRWD

tRWL

tWP

tAWD

tCWD

tCAC

tDS

tDH

tAA

tCLZ

tRAC

tOEA

tOEZ

tOED

tOEH

See Note A

tCWL

Hi-Z

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

Figure 6. Read-Write-Cycle Timing