Functional description

ST1S50

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DocID025723 Rev 4

5

Functional description

The ST1S50 device is based on a “peak current mode”, constant frequency control. The

(0.8 V) providing an error signal that, compared to the output of the current sense amplifier,

controls the ON and OFF time of the power switches.

The main internal blocks are shown in the block diagram in Figure 3. They are:



A fully integrated oscillator that provides the internal clock and the ramp for the slope

compensation avoiding subharmonic instability.



The adjustable soft-start circuitry to limit an inrush current during the start-up phase

source a current on an external RC network.



The trans-conductance error amplifier.



The pulse width modulator and the relative logic circuitry necessary to drive the internal

power switches.



The drivers for embedded high-side and low-side N-channel power MOSFET switches.



The high-side current sensing block.



The low-side current sense to implement diode emulation.



A voltage monitor circuitry (UVLO) that checks the input and internal voltages.



A thermal shutdown block, to prevent a thermal runaway.

Figure 3. Block diagram

Logic

HS

DRV

LS

DRV

PFM

SCP

OVP

PG

DMD

Fsw/2

ref1

ref3

ref1

ref2

Ref

OSC

OTP

INH

UVLO

Int Reg

BG

ref4

EN_SS

REG

VSUM

ref5

SW

BST

VINSW

VINA

COMP

EN_SS

FB

PG

GNDA

GNDP