VT82C586B datasheet(13/69 Pages) ETC

13 / 69 page

9,$7HFKQRORJLHV,QF

VT82C586B

Revision 1.0 May 13, 1997

-7-

Pinouts

ISA Bus Control

Signal Name

Pin No.

I/O

Signal Description

SA[15:0] /

DD[15:0]

20-25, 27-28,

36-38, 40-44

System Address Bus / IDE Data Bus

SA16

System Address Bus

LA23/DCS3B#,

LA22/DCS1B#,

LA21/DCS3A#,

LA20/DCS1A#,

LA[19:17] /

DA[2:0]

63-67, 69-70

Multifunction Pins

ISA Bus Cycles:

Address: The LA[23:17] address lines are bi-directional. These address lines allow

accesses to physical memory on the ISA bus up to 16MBytes.

PCI IDE Cycles:

Chip Select: DCS1A# is for the ATA command register block and corresponds to

CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register

block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the

ATA command register block and corresponds to CS17X# on the primary IDE

connector. DCS3B# is for the ATA command register block and corresponds to

CS37X# on the primary IDE connector.

Disk Address: DA[2:0] are used to indicate which byte in either the ATA command

block or control block is being accessed.

SD[15:8] /

GPI[15:8] /

GPO[15:8]

86-85, 83-80,

78-77

System Data. SD[15:8] provide the high order byte data path for devices residing on

the ISA bus. These pins also function as General Purpose Inputs 15-8 if the

GPIO3_CFG bit is low (pin 92 becomes GPI_RE# for enabling external inputs onto

the SD pins using an external buffer). These pins also function as General Purpose

Outputs 15-8 if the GPIO4_CFG bit is low (pin 136 becomes GPO_WE for control

of an external latch).

SBHE#

System Byte High Enable. SBHE# indicates, when asserted, that a byte is being

transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during

refresh cycles.

IOR#

I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive

data on to the ISA data bus.

IOW#

I/O Write. IOW# is the command to an ISA I/O slave device that the slave may

latch data from the ISA data bus.

MEMR#

123

Memory Read. MEMR# is the command to a memory slave that it may drive data

onto the ISA data bus.

MEMW#

124

Memory Write. MEMW# is the command to a memory slave that it may latch data

from the ISA data bus.

SMEMR#

Standard Memory Read. SMEMR# is the command to a memory slave, under

1MB, which indicates that it may drive data onto the ISA data bus

SMEMW#

Standard Memory Write. SMEMW# is the command to a memory slave, under

1MB, which indicates that it may latch data from the ISA data bus.

BALE

Bus Address Latch Enable. BALE is an active high signal asserted by the

VT82C586B to indicate that the address (SA[19:0], LA[23:17] and the SBHE#

signal) is valid

IOCS16#

125

16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to

indicate that they support 16-bit I/O bus cycles.

MEMCS16#

Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line

low to indicate they support 16-bit memory bus cycles.

IOCHCK#

I/O Channel Check. When this signal is asserted, it indicates that a parity or an

uncorrectable error has occurred for a device or memory on the ISA Bus.

IOCHRDY

I/O Channel Ready. Devices on the ISA Bus negate IOCHRDY to indicate that

additional time (wait states) is required to complete the cycle.

VT82C586B датащи(PDF) 13 Page - List of Unclassifed Manufacturers

VT82C586B датащи(HTML) 13 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

датащи скачать

ссылки URL