A5974AD datasheet(12/49 Pages) STMICROELECTRONICS

12 / 49 page

Functional description

A5974AD

12/49

Doc ID 018762 Rev 1

5.1

Power supply and voltage reference

The internal regulator circuit (shown in Figure 4) consists of a start-up circuit, an internal

voltage pre-regulator, the bandgap voltage reference and the bias block that provides

current to all the blocks. The starter supplies the start-up currents to the entire device when

the input voltage goes high and the device is enabled (inhibit pin connected to ground). The

pre-regulator block supplies the bandgap cell with a pre-regulated voltage, VREG, that has a

very low supply voltage noise sensitivity.

5.2

Voltage monitor

An internal block continuously senses the VCC, VREF and VBG. If the voltages go higher than

their thresholds, the regulator begins operating. There is also a hysteresis on the VCC

(UVLO).

Figure 4.

Internal circuit

5.3

Oscillator and synchronization

Figure 5 shows the block diagram of the oscillator circuit.

The clock generator provides the switching frequency of the device, which is internally fixed

at 500 kHz. The frequency shifter block acts to reduce the switching frequency in case of

strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry

and is the input of the ramp generator and synchronizer blocks.

The ramp generator circuit provides the sawtooth signal, used for PWM control and the

internal voltage feed-forward, while the synchronizer circuit generates the synchronization

signal. The device also has a synchronization pin which can work both as master and slave.

Beating frequency noise is an issue when more than one voltage rail is on the same board.

A simple way to avoid this issue is to operate all the regulators at the same switching

frequency.

The synchronization feature, of a set of the A5974AD, is simply obtained by connecting

together their SYNCH pins. The device with the highest switching frequency is the master,

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