STTS2004 datasheet(37/58 Pages) STMICROELECTRONICS

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STTS2004

SPD EEPROM operation

Figure 14. Write cycle polling flowchart using ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum Write time (tw) is

shown in Table 33, but the typical time is shorter. To make use of this, a polling sequence

can be used by the bus master.

5.6

Read operations

Read operations are performed independently of whether a hardware or software protection

has been set.

The device has an internal address counter which is incremented each time a byte is read.

5.6.1

Random address read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 15) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the RW bit set to 1. The device

acknowledges this, and outputs the contents of the addressed byte. The bus master must

not acknowledge the byte, and terminates the transfer with a Stop condition.

WRITE cycle

in progress

AI01847d

operation is

addressing the

memory

Start condition

Device select

with RW = 0

ACK

returned

YES

ReStart

Stop

Data for the

WRITE operation

Device select

with RW = 1

Send address

and receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YES

Start

condition

Continue the

WRITE operation

Continue the

Random READ operation

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