TAS5721 datasheet(21/78 Pages) TI1

21 / 78 page

Digital Audio

Processor

(DAP)

I C Control Port

Internal Register/State Machine Interface

Stereo Headphone

Amplifier

PVDD

DVDD

MCLK Monitoring

and Watchdog

Charge Pump

AVDD

PDN

RST

SPK_OUTA

SPK_OUTD

SDIN

MCLK

SCLK

LRCLK

DR_INA

DR_INB

DR_VSS

DR_OUTA

DR_OUTB

TAS5721

SCL

SDA

Serial Audio Port

(SAP)

Sample Rate

Auto-Detect

PLL

Open Loop 4 Channel

PWM Amplifier

Sensing and

Protection

Temperature

Short Circuits

PVDD Voltage

Output Current

Fault Notification

SPK_OUTB

SPK_OUTC

Sample Rate

Converter

(SRC)

Digital to PWM

Converter

(DPC)

Click and Pop

Suppression

3 Ch. PWM

Modulator

Noise Shaping

Power-On Reset

(POR)

Internal Voltage Supplies

Internal Regulation and Power Distribution

DR_CP

DR_CN

DRVDD

TAS5721

www.ti.com

SLOS739A – JULY 2012 – REVISED MARCH 2016

Product Folder Links: TAS5721

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9 Detailed Description

9.1 Overview

The TAS5721 device is an efficient stereo I2S input Class-D audio power amplifier with a digital audio processor

and a DirectPath headphone/line driver.

The digital audio processor of the device uses noise shaping and customized correction algorithms to achieve a

great power efficiency and high audio performance. Also, the device has up to eight Equalizers per channel and

two -band configurable Dynamic Range Control (DRC).

The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal

voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of

the device enables its use in a multitude of applications.

The device has an integrated DirectPath headphone amplifier / line driver to increase system level integration

and reduce total solution costs. DirectPath architecture eliminates the requirement for external dc-blocking output

capacitors.

The TAS5721 device is a slave-only device that is controlled by a bidirectional I2C interface that supports both

100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control

interface is used to program the registers of the device and read the device status. The PWM of this device

operates with a carrier frequency between 384 kHz and 354 kHz, depending the sampling rate. This device

allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using a sampling frequency of

44.1 kHz or 48 kHz.

This device can be used in three different modes of operation, Stereo BTL Mode, Single Filter PBTL Mono Mode,

and 2.1 Mode.

9.2 Functional Block Diagram

Figure 48. Functional Block Diagram

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