PC87366 datasheet(152/240 Pages) NSC

152 / 240 page

8.0 ACCESS.bus Interface (ACB) (Continued)

152

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8.3.6

ACB Own Address Register (ACBADDR)

This is a byte-wide register that holds the ACB ACCESS.bus address. The reset value of this register is undefined.

Location:

Offset 04h

Type:

R/W

8.3.7

ACB Control Register 2 (ACBCTL2)

This register enables/disables the functional block and determines the ACB clock rate.

Location:

Offset 05h

Type:

R/W

Bit

76543210

Name

SAEN

ADDR

Reset

Bit

Description

SAEN (Slave Address Enable)

0: ACB does not check for an address match with ADDR field

1: ADDR field holds a valid address and enables the match of ADDR to an incoming address byte

6-0

ADDR (Own Address). These bits hold the 7-bit device address. When in slave mode, the ﬁrst 7 bits received

after a Start Condition are compared with this ﬁeld (ﬁrst bit received is compared with bit 6, and the last bit with

bit 0). If the address ﬁeld matches the received data and SAEN (bit 7) is 1, a match is declared.

Bit

6543210

Name

SCLFRQ

ENABLE

Reset

0000000

Bit

Description

7-1

SCLFRQ (SCL Frequency). This ﬁeld deﬁnes the SCL period (low and high time) when the device serves as a

bus master. The clock low and high times are deﬁned as follows:

tSCLl =tSCLh = 2*SCLFRQ*tCLK

where tCLK is the module input clock cycle, as deﬁned in the Device Architecture and Conﬁguration chapter.

SCLFRQ can be programmed to values in the range of 00010002 (810) through 11111112 (12710). Using any

other value has unpredictable results.

Enable

0: ACB disabled, ACBCTL1, ACBST and ACBCST cleared, and clocks halted

1: ACB enabled

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