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PC87366 датащи(PDF) 150 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали PC87366
подробное описание детали  128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports
PDF  240 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87366 датащи(HTML) 150 Page - National Semiconductor (TI)

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8.0 ACCESS.bus Interface (ACB) (Continued)
150
www.national.com
8.3.4
ACB Control Status Register (ACBCST)
This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB
functions. On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared.
Location:
Offset 02h
Type:
Varies per bit
Bit
76543210
Name
Reserved
TGSCL
TSDA
GCMTCH
MATCH
BB
BUSY
Reset
0
0
0
X
0000
Bit
Type
Description
7-6
Reserved
5
R/W
TGSCL (Toggle SCL Line). Enables toggling the SCL line during error recovery.
0: Clock toggle completed
1: When the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL
while SDA is high is ignored.
4RO
TSDA (Test SDA Line). This bit reads the current value of the SDA line. It can be used while recovering
from an error condition in which the SDA line is constantly pulled low by an out-of-sync slave. Data written
to this bit is ignored.
3RO
GCMTCH (Global Call Match)
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition)
1: In slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start
Condition) is 00h.
2RO
MATCH (Address Match)
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition)
1: ACBADDR.SAEN is set and the first 7 bits of the address byte (the first byte transferred after a Start
Condition) match the 7-bit address in the ACBADDR register.
1
R/W1C BB (Bus Busy)
0: Writing 1, ACB disabled, or Stop Condition detected
1: Bus active (a low level on either SDA or SCL), or Start Condition
0RO
Busy. This bit should always be written 0. This bit indicates the period between detecting a Start Condition
and completing receipt of the address byte. After this, the ACB is either free or enters slave mode.
0: Completion of any state below or ACB disabled
1: ACB is in one of the following states:
Generating a Start Condition
Master mode (ACBST.MASTER is set)
Slave mode (ACBCST.MATCH or ACBCST.GCMTCH set).



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