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PC87364 датащи(PDF) 43 Page - National Semiconductor (TI) |
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PC87364 датащи(HTML) 43 Page - National Semiconductor (TI) |
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43 / 180 page ![]() 2.0 Device Architecture and Configuration (Continued) 43 www.national.com 2.9 SUPERI/O CONFIGURATION REGISTERS This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h - 2Eh). See Table 16 for a summary and directory of these registers. Table 16. SuperI/O Configuration Registers Index Mnemonic Register Name Power Well Type Section 20h SID SuperI/O ID VDD RO 2.8.1 21h SIOCF1 SuperI/O Configuration 1 VDD R/W 2.8.2 22h SIOCF2 SuperI/O Configuration 2 VDD R/W 2.8.3 23h SIOCF3 SuperI/O Configuration 3 VDD R/W 2.8.4 24h SIOCF4 SuperI/O Configuration 4 VDD R/W 2.8.5 25h SIOCF5 SuperI/O Configuration 5 VDD R/W 2.8.6 27h SRID SuperI/O Revision ID VDD RO 2.8.7 28h SIOCF8 SuperI/O Configuration 8 VDD R/W 2.8.8 2Ah SIOCFA SuperI/O Configuration A VPP R/W 2.8.9 2Bh SIOCFB SuperI/O Configuration B VPP R/W 2.8.10 2Ch SIOCFC SuperI/O Configuration C VPP R/W 2.8.11 2Dh SIOCFD SuperI/O Configuration D VPP R/W 2.8.12 2Eh Reserved exclusively for National use |
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