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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STGAP1S датащи(PDF) 43 Page - STMicroelectronics |
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STGAP1S датащи(HTML) 43 Page - STMicroelectronics |
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43 / 67 page  DocID027190 Rev 3 43/67 STGAP1S SPI interface 67 8 SPI interface The IC communicates with an external MCU through a 16-bit SPI. This interface is used to set the device parameters and for advanced diagnostic. The SPI I/O pins are: CS: chip select (active low) CK: serial clock SDI: serial data input (MOSI) SDO: serial data output (MISO). The interface is compliant with the SPI standard CPHA = 1 and CPOL = 0 (serial data is sampled on CK falling edge and it is updated on CK rising edge, at CS falling edge the CK signal must be low) as shown in Figure 20. Figure 20. SPI timings The SPI interface can work up to 5 Mbps and provides the daisy chain feature. In order to guarantee a safe operation and robustness to electrical noise, the number of rising edges within a CS negative pulse must be multiple of 16, otherwise the communication cycle is ignored and a communication failure is indicated forcing high the SPI_ERR flag. Any number of the STGAP1S can be connected in daisy chain, and only 4 lines for the SPI and one for the SD are required in order to guarantee access to status and configuration registers of each device. An example of daisy chain configuration is shown in Figure 21. CK SDI SDO CS MSB LSB LSB N-1 N-2 MSB HiZ N-1 N-2 tsetCS tenSDO tsetSDI tholSDI tvSDO tholSDO tfCK trCK tlCK thCK tdisSDO tholCS tdesCS MSB SD tSDLCSL tCSHSDH (Not required for NOP and read operations) |
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