L6564H

Pin connection

Doc ID 022960 Rev 2

7/35

3

Pin connection

Figure 2.

Pin connection

AM11476v1

HVS

CS

COMP

MULT

VFF

GD

GND

ZCD

PFC_OK

INV

Vcc

N.C.

2

3

4

1

5

6

78

10

11

12

13

14

N.C.

N.C.

9

Table 3.

Pin description

n°

Name

Function

1INV

Inverting input of the error amplifier. The information on the output voltage of the PFC pre-

regulator is fed into the pin through a resistor divider. The pin normally features high

impedance.

2COMP

Output of the error amplifier. A compensation network is placed between this pin and INV (pin

1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To

avoid an uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls

below 2.4 V the gate driver output is inhibited (burst-mode operation).

3MULT

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor

divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used

also to derive the information on the RMS mains voltage.

4CS

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,

the resulting voltage is applied to this pin and compared with an internal reference to determine

MOSFET turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to

boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily

stops the converter and limits the stress of the power components.

5VFF

connected from the pin to GND. They complete the internal peak-holding circuit that derives the

information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak

voltage on the MULT pin (3), compensates the control loop gain dependence on the mains

voltage. Never connect the pin directly to GND but with a resistor ranging from 100 K

Ω

(minimum) to 2 M

Ω (maximum).