SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010

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POST OFFICE BOX 655303

Significantly Reduces Power Dissipation

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

and Power Down

Generator/Checker

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Plastic (NT)

and Ceramic (JT) DIPs

description

The ’ABT853 8-bit to 9-bit parity transceivers are

designed for communication between data buses.

When data is transmitted from the A bus to the

B bus, a parity bit is generated. When data is

transmitted from the B bus to the A bus with its

corresponding parity bit, the open-collector

parity-error (ERR) output indicates whether or not

an error in the B data has occurred. The

output-enable (OEA and OEB) inputs can be used

to disable the device so that the buses are

effectively isolated. The ’ABT853 transceivers

provide true data at their outputs.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports

with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the

latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from

the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the

designer more system diagnostic capability.

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright © 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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OEA

A1

A2

A3

A4

A5

A6

A7

A8

ERR

CLR

GND

B1

B2

B3

B4

B5

B6

B7

B8

PARITY

OEB

LE

SN54ABT853 . . . JT OR W PACKAGE

SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

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25

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B3

B4

B5

NC

B6

B7

B8

A3

A4

A5

NC

A6

A7

A8

426

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SN54ABT853 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection