PC97317 datasheet(13/272 Pages) NSC

13 / 272 page

Table of Contents

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8.7.2

Extended Control Register 1 (EXCR1) ...................................................................... 208

8.7.3

Line Control Register (LCR) and Bank Select Register (BSR) .................................. 209

8.7.4

Extended Control and Status Register 2 (EXCR2) .................................................... 209

8.7.5

Reserved Register ..................................................................................................... 209

8.7.6

TX_FIFO Current Level Register (TXFLV) ................................................................ 209

8.7.7

RX_FIFO Current Level Register (RXFLV) ............................................................... 210

8.8

BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 210

8.8.1

Module Revision ID Register (MRID) ........................................................................ 210

8.8.2

Shadow of Line Control Register (SH_LCR) ............................................................. 210

8.8.3

Shadow of FIFO Control Register (SH_FCR) ............................................................ 211

8.8.4

Line Control Register (LCR) and Bank Select Register (BSR) .................................. 211

8.9

UART1 REGISTER BITMAPS ................................................................................................. 211

9.0

General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip

Select Output Signals

9.1

GPIO PORT ACTIVATION ...................................................................................................... 215

9.2

GPIO CONTROL REGISTERS ............................................................................................... 215

9.2.1

Special GPIO Signal Features ................................................................................... 215

9.2.2

Reading and Writing to GPIO Pins ............................................................................ 215

9.2.3

Multiplexed GPIO Signals .......................................................................................... 215

9.2.4

Multiplexed GPIO Signal Selection ............................................................................ 215

9.3

PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS ......................................................... 216

10.0

Power Management (Logical Device 8)

10.1

POWER MANAGEMENT OPTIONS ....................................................................................... 218

10.1.1

Configuration Options ................................................................................................ 218

10.1.2

WATCHDOG Feature ................................................................................................ 218

10.2

POWER MANAGEMENT REGISTERS ................................................................................... 218

10.2.1

Power Management Index Register .......................................................................... 218

10.2.2

Power Management Data Register ........................................................................... 219

10.2.3

Function Enable Register 1 (FER1) ........................................................................... 219

10.2.4

Function Enable Register 2 (FER2) ........................................................................... 219

10.2.5

Power Management Control Register (PMC1) .......................................................... 220

10.2.6

Power Management Control 2 Register (PMC2) ....................................................... 221

10.2.7

Power Management Control 3 Register (PMC3) ....................................................... 221

10.2.8

WATCHDOG Time-Out Register (WDTO) ................................................................ 222

10.2.9

WATCHDOG Configuration Register (WDCF) .......................................................... 222

10.2.10 WATCHDOG Status Register (WDST) ...................................................................... 223

10.2.11 PM1 Event Base Address Register (Bits 7-0) ............................................................ 223

10.2.12 PM1 Event Base Address Register (Bits 15-8) .......................................................... 223

10.2.13 PM Timer Base Address (Bits 7-0) ............................................................................ 223

10.2.14 PM Timer Base Address Register (Bits 15-8) ............................................................ 224

10.2.15 PM1 Control Base Address Register (Bits 7-0) ......................................................... 224

10.2.16 PM1 Control Base Address Register (Bits 15-8) ....................................................... 224

10.2.17 General Purpose Status Base Address Register (Bits 7-0) ....................................... 224

10.2.18 General Purpose Status Base Address Register (Bits 15-8) ..................................... 224

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