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PC87309VLJ датащи(PDF) 181 Page - National Semiconductor (TI) |
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PC87309VLJ датащи(HTML) 181 Page - National Semiconductor (TI) |
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181 / 192 page ![]() Device Specifications 181 www.national.com 10.3.11 ECP DMA Timing 1. One DMA transaction takes six clock cycles. 2. tCP is defined in Section 10.3.2 on page 171. 3. Only in case of pending DRQ. 4. The active edge of RD or WR and TC is recognized only when DACK is active. Symbol Parameter Min Max Unit tKIP DACK Inactive Pulse Width 25 nsec tKKP DACK Active Pulse Width 65 nsec tKQP DACK Active Edge to DRQ Inactive12 65 + (6 x 32 x tCP) nsec tQKP DRQ to DACK Active Edge 10 nsec tQPP DRQ Period 330 nsec tQQP DRQ Inactive Non-Burst Pulse Width 300 4003 nsec tQRP DRQ to RD, WR Active 15 nsec tRQP RD, WR Active Edge to DRQ Inactive4 65 nsec tTQP TC Active Edge to DRQ Inactive 75 nsec tTT TC Active Pulse Width 50 nsec tQKP tKQP tQPP tTT tKKP tQRP tQQP tKIP tRQP tTQP DRQ DACK RD, WR TC |
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