PC87309 datasheet(94/192 Pages) NSC

94 / 192 page

Parallel Port (Logical Device 1)

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Bit 5 - Reserved

Bit 6 - Channel Address Enable

When this bit is 1, mode is 011, direction is backward,

there is an input command (BUSY is 0), and bit 7 of the

data is 1, the command is written into the FIFO.

Bit 7 - SPP Compatibility

See “Bits 7-5 - ECP Mode Control” on page 92 for a de-

scription of each mode.

0: Modes 000, 001 and 100 are identical to ECP.

1: Modes 000 and 001 of the ECP are identical with

Compatible and Extended modes of the SPP (see

Section 4.1 "PARALLEL PORT CONFIGURATION"

on page 79), and mode 100 of the ECP is compati-

ble with EPP mode.

Modes 000, 001 and 100 differ as follows:

000, 001 and 100 – Reading DCR returns pin values of

bits 3-0.

000 and 001 – Reading DCR returns 1 for bit 5.

000, or 001 or 100 when bit 5 of DCR is 0 (forward di-

rection) – Reading DATAR returns register latched

value instead of pin values.

000, 001, and 100, when bit 4 of DCR is 0 – IRQx is

ﬂoated.

001 – IRQx is a level interrupt generated on the trailing

edge of ACK. Bit 2 of the DSR is the IRQ status bit

(same behavior as bit 2 of the STR).

4.5.18

Control4 Register

Upon reset this register is initialized to 00000111.

This register enables control of the fairness mechanism of

the DMA by programming the maximum number of bus cy-

cles that the parallel port DMA request signals can remain

active, and the minimum number of clock cycles that they

will remain inactive after they were deactivated.

Bits 2- 0 - Parallel Port DMA Request Active Time

This field specifies the maximum number of consecutive

bus cycles that the parallel port DMA signals can remain

active.

The default value is 111, which specifies 32 cycles.

When these bits are 0, the number is 1 cycle.

Otherwise, the number is 4(n+1) where n is the value of

these bits.

Bit 3 - Reserved

Bits 6-4 - Parallel Port DMA Request Inactive Time

This field specifies the minimum number of clock cycles

that the parallel port DMA signals remain inactive after

being deactivated by the fairness mechanism.

The default value is 000, which specifies 8 clock cycles.

Otherwise, the number of clock cycles is 8 + 32n, where

n is the value of these bits.

Bit 7 - Reserved

4.5.19

PP Confg0 Register

Upon reset this register is initialized to 00h.

Bits 1, 0 - ECP DMA Channel Number

These bits identify the ECP DMA channel number, as

reflected on bits 1 and 0 of the ECP CNFGB register.

See Section 4.5.11 "Configuration Register B (CNFGB)"

on page 91. Actual ECP DMA routing is controlled by

the DMA channel select register (index 74h) of this log-

ical device.

Microsoft’s ECP protocol and ISA interface standard de-

fine bits 1 and 0 of CNFGB as shown in TABLE 4-7

"ECP Mode DMA Selection" on page 91.

Bit 2 - Paper End (PE) Internal Pull-up or Pull-down Resistor

Select

0: PE has a nominal 25 K

Ω internal pull-down resis-

tor.

1: PE has a nominal 25 K

Ω internal pull-up resistor.

Bits 5- 3 - ECP IRQ Number

These bits identify the ECP IRQ number, as reflected on

bits 5 through 3 of the ECP CNFGB register. See Sec-

tion 4.5.11 "Configuration Register B (CNFGB)" on

page 91. Actual ECP IRQ routing is controlled by inter-

rupt select register (index 70h) of this logical device.

Microsoft’s ECP protocol and ISA interface standard de-

fines bits 5 through 3 of CNFGB, as shown in TABLE

4-8 "ECP Mode Interrupt Selection" on page 91.

Bit 6 - Demand DMA Enable

If enabled, DRQ is asserted when a FIFO threshold of 4

is reached or when flush-time-out expires, except when

DMA fairness prevents DRQ assertion. The threshold of

4 is for four empty entries forward and for four valid en-

tries backward.

76543210

Reset

Required

Control4 Register

Offset 04h

Reserved

PP DMA Request Inactive Time

PP DMA Request

Second Level

Active Time

76543210

Reset

Required

PP Confg0 Register

Offset 05h

ECP DMA Channel Number

PE Internal Pull-up or Pull-down

ECP IRQ Number

Demand DMA Enable

Bit 3 of CNFGA

Second Level

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