PCKV857ADGV datasheet(5/13 Pages) PHILIPS

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Philips Semiconductors

Product data

PCKV857A

100-250 MHz differential 1:10 clock driver

2003 Jul 31

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIK

Input voltage, all inputs

VDDQ = 2.3 V, II = -18 mA

—

−1.2

VDDQ = min to max, IOH = -1 mA

VDDQ − 0.1

—

VOH

HIGH-level output voltage

VDDQ = 2.3 V, IOH = -12 mA

1.7

—

VDDQ = min to max, IOL = 1 mA

—

0.1

VOL

LOW-level output voltage

VDDQ = 2.3 V, IOL = 12 mA

—

0.6

Input current

VDDQ = 2.7 V, VI = 0 V to 2.7 V

—

±10

µA

IOZ

HIGH-impedance-state output current

VDDQ = 2.7 V, VO = VDDQ or GND

—

±10

µA

IDDPD

Power-down current on VDDQ + AVDD

CLK and CLK = 0 MHz,

PWRDWN = LOW;

Σ of IDD and AIDD

—

100

µA

IDD

Dynamic current on VDDQ

fO = 67 MHz to 190 MHz

—

200

300

AIDD

Supply current on AVDD

fO = 67 MHz to 190 MHz

—

Input capacitance

VCC = 2.5 V, VI = VCC or GND

2.8

NOTE:

1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs.

2. All typical values are at respective nominal VDDQ.

3. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature.

SYMBOL

PARAMETER

MIN

MAX

UNIT

fCK

Operating clock frequency

100

250

MHz

Input clock duty cycle

Stabilization time1

100

—

µs

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.

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