Bit 4

This bit is the Break Interrupt (BI) indicator Bit 4 is set

to a logic 1 whenever the received data input is held in the

Spacing (logic 0) state for longer than a full word transmis-

CPU reads the contents of the Line Status Register or when

the next valid character is loaded into the Receiver Buffer

Register In the FIFO Mode this condition is associated with

the particular character in the FIFO it applies to It is re-

vealed to the CPU when its associated character is at the

top of the FIFO When break occurs only one zero character

is loaded into the FIFO The next character transfer is en-

abled after SIN goes to the marking state and receives the

next valid start bit

Note

Bits 1 through 4 are the error conditions that produce a Receiver Line

Status interrupt whenever any of the corresponding conditions are

detected and the interrupt is enabled

Bit 5

This bit is the Transmitter Holding Register Empty

(THRE) indicator In the 16450 mode bit 5 indicates that the

associated serial channel is ready to accept a new charac-

ter for transmission In addition this bit causes the DUART

to issue an interrupt to the CPU when the Transmit Holding

Register Empty Interrupt enable is set high The THRE bit is

set to a logic 1 when a character is transferred from the

Transmitter Holding Register into the Transmitter Shift Reg-

ister The bit is reset to logic 0 concurrently with the loading

of the Transmitter Holding Register by the CPU In the FIFO

mode this bit is set when the XMIT FIFO is empty it is

cleared when at least 1 byte is written to the XMIT FIFO

Bit 6

This bit is the Transmitter Empty (TEMT) indicator Bit

6 is set to a logic 1 whenever the Transmitter Holding Regis-

ter (THR) and the Transmitter Shift Register (TSR) are both

empty It is reset to a logic 0 whenever either the THR or

TSR contains a data character In the FIFO mode this bit is

set to one whenever the transmitter FIFO and shift register

are both empty

Bit 7

In the 16450 Mode this is a 0 In the FIFO Mode LSR7

is set when there is at least one parity error framing error or

break indication in the FIFO LSR7 is cleared when the CPU

reads the LSR if there are no subsequent errors in the

FIFO

Note

The Line Status Register is intended for read operations only Writing

to this register is not recommended as this operation is only used for

factory testing In the FIFO mode the user must load a data byte into

the Rx FIFO in order to write to LSR2–4 LSR0 and LSR7 cannot be

written to in the FIFO mode

85 FIFO CONTROL REGISTER

This is a write only register at the same location as the IIR

(the IIR is a read only register) This register is used to en-

able the FIFOs clear the FIFOs set the RCVR FIFO trigger

level and select the type of DMA signalling

Bit 0

Writinga1to FCR0 enables both the XMIT and RCVR

FIFOs Resetting FCR0 will clear all bytes in both FIFOs

When changing from FIFO Mode to 16450 Mode and vice

versa data is automatically cleared from the FIFOs This bit

must be a 1 when other FCR bits are written to or they will

not be programmed

Bit 1

Writinga1to FCR1 clears all bytes in the RCVR FIFO

and resets its counter logic to 0 The shift register is not

cleared The 1 that is written to this bit position is self-clear-

ing

Bit 2

Writinga1to FCR2 clears all bytes in the XMIT FIFO

and resets its counter logic to 0 The shift register is not

cleared The 1 that is written to this bit position is self-clear-

ing

Bit 3

Writinga1to FCR3 causes RXRDY and TXRDY oper-

RXRDY Mode 0

least 1 character in the RCVR FIFO or RCVR Buffer Regis-

ter the RXRDY pin will go low active Once active the

RXRDY pin will go inactive when there are no more charac-

ters in the FIFO or Buffer Register

TABLE IV Baud Rates Divisors and Crystals

18432 MHz Crystal

3072 MHz Crystal

18432 MHz Crystal

Baud Rate

Decimal Divisor

Percent Error

Decimal Divisor

Percent Error

Decimal Divisor

Percent Error

50

2304

3840

23040

75

1536

2560

15360

110

1047

0026

1745

0026

10473

1345

857

0058

1428

0034

8565

150

768

1280

7680

300

384

640

3840

600

192

320

1920

1200

96

160

920

1800

64

107

0312

640

2000

58

069

96

576

2400

48

80

480

3600

32

53

0628

320

4800

24

40

240

7200

16

27

123

160

9600

12

20

120

19200

6

10

60

38400

3

5

30

56000

2

286

21

204

128000

9

Note

For baud rates of 250k 300k 375k 500k 750k and 15M using a 24 MHz crystal causes minimal error

17