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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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NSC800 датащи(PDF) 22 Page - National Semiconductor (TI) |
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NSC800 датащи(HTML) 22 Page - National Semiconductor (TI) |
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22 / 76 page  90 Timing and Control (Continued) A reset to the CPU will force both IFF1 and IFF2 to the reset state disabling maskable interrupts They can be enabled by an EI instruction at any time by the programmer When an EI instruction is executed any pending interrupt requests will not be accepted until after the instruction following EI has been executed This single instruction delay is necessary in situations where the following instruction is a return instruc- tion and interrupts must not be allowed until the return has been completed The EI instruction sets both IFF1 and IFF2 to the enable state When the CPU accepts an interrupt both IFF1 and IFF2 are automatically reset inhibiting further interrupts until the programmer wishes to issue a new EI instruction Note that for all the previous cases IFF1 and IFF2 are always equal The function of IFF2 is to retain the status of IFF1 when a non-maskable interrupt occurs When a non-maskable inter- rupt is accepted IFF1 is reset to prevent further interrupts until reenabled by the programmer Thus after a non-mask- able interrupt has been accepted maskable interrupts are disabled but the previous state of IFF1 is saved by IFF2 TLC5171 – 27 FIGURE 17 Interrupt Mode 2 22 |
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