STM32F303VB datasheet(19/148 Pages) STMICROELECTRONICS

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DocID023353 Rev 13

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STM32F303xB STM32F303xC

Functional overview

3.10

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

3.11

Direct memory access (DMA)

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-

memory and memory-to-peripheral transfers. The DMA controller supports circular buffer

management, avoiding the generation of interrupts when the controller reaches the end of

the buffer.

Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with

software trigger support for each channel. Configuration is done by software and transfer

sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,

DAC and ADC.

3.12

Interrupts and events

3.12.1

Nested vectored interrupt controller (NVIC)

The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller

(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Closely coupled NVIC core interface

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

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