Day of Week Counter

The day of week counter increments as the time rolls from

2359 to 0000 (1159 PM to 1200 AM in 12-hour mode) It

counts from 1 to 7 and rolls back to 1 Any day of the week

may be specified as day 1

Clock Setting RegisterInterrupt Register

The interrupt select bit in the control register determines

which of these two registers is accessible to the processor

at address 15 Normal clock and interrupt timing operations

will always continue regardless of which register is selected

onto the bus The layout of these registers is shown in

Table II

The clock setting register is comprised of three separate

functions

a) leap year counter bits 2 and 3

b) AMPM indicator bit 1

c) 12-hour mode set bit 0 (see Table IIA)

The leap year counter is a 2-stage binary counter which

is clocked by the months counter It changes state as the

time rolls over from 1159 on December 31 to 0000 on

January 1

The counter should be loaded with the ‘number of years

since last leap year’ eg if 1980 was the last leap year a

clock programmed in 1983 should have 3 stored in the leap

year counter If the clock is programmed during a leap year

then the leap year counter should be set to 0 The contents

of the leap year counter can be read by the mP

The AMPM indicator returns a logic 0 for AM and a logic 1

for PM It is clocked when the hours counter rolls from 1159

to 1200 in 12-hour mode In 24-hour mode this bit is set to

logic 0

The 1224-hour mode set determines whether the hours

counter counts from 1 to 12 or from 0 to 23 It also controls

the AMPM indicator enabling it for 12-hour mode and forc-

ing it to logic 0 for the 24-hour mode The 1224-hour mode

bit is set to logic 0 for 12-hour mode and it is set to logic 1

for 24-hour mode

IMPORTANT NOTE

Hours mode and AMPM bits cannot

be set in the same write operation See the section on Ini-

tialization (Methods of Device Operation)

for a suggested

setting routine

All bits in the clock setting register may be read by the proc-

essor

The interrupt register controls the operation of the timer for

interrupt output The processor programs this register for

single or repeated interrupts at the selected time intervals

The lower three bits of this register set the time delay period

that will occur between interrupts The time delays that can

be programmed and the data words that select these are

outlined in Table IIB

Data bit 3 of the interrupt register sets for either single or

repeated interrupts logic 0 gives single mode logic 1 sets

for repeated mode

Using the interrupt is described in the Device Operation sec-

tion

TABLE IIA Clock Setting Register Layout

Function

Data Bits Used

Comments

Access

DB3

DB2

DB1

DB0

Leap Year Counter

X

X

0 Indicates a Leap Year

RW

AMPM Indicator (12-Hour Mode)

X

RW

0 in 24-Hour Mode

1224-Hour Select Bit

X

RW

TABLE IIB Interrupt Control Register

Function

Comments

Control Word

DB3

DB2

DB1

DB0

No Interrupt

Interrupt output cleared

X

0

0

0

startstop bit set to 1

01 Second

01

0

0

1

05 Second

01

0

1

0

1 Second

01

0

1

1

5 Seconds

01

1

0

0

10 Seconds

01

1

0

1

30 Seconds

01

1

1

0

60 Seconds

01

1

1

1

with first interrupt (ie timing errors do not accumulate)

7