GRAYCHIP,INC.

- 16 -

FEBRUARY 18, 1998

GC1012A DIGITAL TUNER

DATA SHEET REV 0.1

This document contains information which may be changed at any time without notice

3.6

OUTPUT STATUS REGISTER

This register contains flags and status information for the output samples.

ADDRESS 9:

Output Status Register

BIT

TYPE

NAME

DESCRIPTION

0

R/W

READY

Tells the chip that the user is ready to capture an output sample. The chip clears

this bit when it has captured the sample. See Notes below.

1

R/Clear

MISSED

The chip sets this bit high if a new output sample was ready but the user had not

set READY high. This lets the user know if a sample has been missed. This bit is

cleared by writing a 0 to the bit. Attempting to write a 1 to this bit does nothing.

2

R/W

INT_ENABLE

This bit is used to turn on the interrupt output. If this bit is off the INT output pin is

forced high. When this bit is high the INT output pin is equal to READY. When

READY goes low, meaning that a new sample has been captured, the INT pin will

go low. If INT is tied to a processorÕs interrupt input, then the processor will be

interrupted whenever a new sample is ready.

3

R/W

-

Unused

4

R/W

OFLOW_MODE

This bit sets the mode of the OFLOW output. When OFLOW_MODE is low the

OFLOW output is an inverted version of OVERFLOW (see bit 6 below). If

OFLOW_MODE and OFLOW_ENABLE are high, then the OFLOW output pulses

low for one clock cycle each time there is an overflow.

5

R/W

OFLOW_ENABLE

This bit enables the overflow modes. If this bit is low, then OVERFLOW (see bit 6

below) will not be set and the OFLOW output will not go low. This bit does not affect

the overflow detection and saturation logic in the gain circuit.

6

R/Clear

OVERFLOW

The chip sets this bit when an overflow occurs and OFLOW_ENABLE is turned on.

This bit can be used to indicate if the gain is set too high. This bit stays high until

the user clears it. The bit is cleared by writing a 0 to it. Attempting to write a 1 to

this bit does nothing.

7

R/W

POWER_DOWN

This bit is used to put the chip into a power down (standby) mode. In this mode the

internal clock rate is reduced to approximately 1 KHz. All control register settings

are preserved, but the output data will be invalid.

The READY signal is used to capture output samples and to read them into an external processor.

The user captures outputs by setting the READY bit and then waiting for the bit to be cleared by the chip.

When the bit goes low the processor can read the samples out of the I and Q output registers described in

section 3.9. The processor can wait for READY to go low by either continuously reading this register, or it

can use the interrupt output INT to tell it when the sample is ready. To use the interrupt output mode the

user must tie the INT output pin from the chip to an interrupt input of the processor. The processor can then

capture samples by setting READY and then setting INT_ENABLE (INT_ENABLE should be set after

READY in order to avoid a spurious interrupt due to the interrupt being enabled before READY has settled

to its high state). The processor will be interrupted when READY goes low again. When it is interrupted the

processor can turn off INT_ENABLE, read the I/Q outputs, and then start over again.

The MISSED flag is provided to let the processor know if it has taken too long to read the I/Q

samples before rearming the READY bit. If the processor wants to use the MISSED flag it should clear the

flag the first time it sets the READY bit and then check it after setting the READY bit thereafter. The READY

bit is set and the MISSED bit cleared by writing a 01(hex) to this register. The READY bit is set and the

MISSED bit is left alone by writing a 03(hex) to this register.

NOTE: The READY bit will not be cleared if the sample is captured while the user is setting the

READY bit. This will cause the READY bit to stay high after the output is captured and will not allow the chip

to capture any more samples until the bit is cleared and set again. The user can detect this incorrect ÒreadyÓ

state by always clearing the MISSED bit when setting the READY bit. The incorrect state is detected if

MISSED goes high when READY is high. The work-around to guarantee capturing an output sample is to

always clear READY before setting it.