FS6330 datasheet(3/6 Pages) ETC

3 / 6 page

AMERICAN MICROSYSTEMS, INC.

May 2000

5.23.00

Preliminary information

FS6330

LAN Hub Clock Generator IC

Table 5: DC Electrical Specifications

Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal

characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are

± 3σfrom typical. Negative currents indicate current flows out of the device.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Overall

Supply Current, Dynamic, with Loaded

Outputs

IDD

All 3.3V supplies = 3.465V

X1 Crystal Oscillator Feedback

Threshold Bias Voltage

VTH

0.5VDD

High-Level Input Current

IIH

VIH = 3.3V

µA

Low-Level Input Current

IIL

VIL = 0V

-32

µA

Crystal Loading Capacitance *

CL(xtal)

As seen by an external crystal connected

to XIN and XOUT

13.5

22.5

Input Loading Capacitance *

CL(XIN)

As seen by an external clock driver on

XOUT; XIN unconnected

X2 Crystal Oscillator Drive

High Level Output Source Current

IOH

VI = 3.3V, VO = 0V

-8

Low Level Output Sink Current

IOL

VI = 0V, VO = 3.3V

Clock Outputs

High-Level Output Source Current

IOH

VO = 2.4V

Low-Level Output Sink Current

IOL

VO = 0.4V

Output Impedance

Measured at 1.5V

Ω

Short Circuit Output Source Current

IOSH

VO = 0V; shorted for 30s, max.

Short Circuit Output Sink Current

IOSL

VO = 3.3V; shorted for 30s, max.

Table 6: AC Timing Specifications

Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and

are not currently production tested to any specific limits. MIN and MAX characterization data are

± 3σfrom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Clock Outputs

Duty Cycle *

Ratio of high pulse width to one clock period,

measured at 1.5V

Clock Skew *

tsk(o)

CLKB1 to CLKB4 at 1.5V

250

Jitter, Long Term (

τ)) *

tj(LT)

On rising edges 500

µs apart at 1.5V relative to an

ideal clock, CL=15pF, all PLLs active

Jitter, Period (peak-peak) *

tj(∆P)

From rising edge to rising edge at 1.5V, CL=15pF,

all PLLs active

150

Rise Time *

Measured @ 0.4V – 2.4V; CL=15pF

1.2

Fall Time *

Measured @ 2.4V – 0.4V; CL=15pF

1.2

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