SPC560P54x datasheet(26/105 Pages) STMICROELECTRONICS

26 / 105 page

Introduction

SPC56xP54x, SPC56xP60x

26/105

DocID18340 Rev 6

–

Watchpoint triggering, watchpoint triggers program tracing

–DDR



Auxiliary Output Port

–

4 MDO (Message Data Out) pins

–

MCKO (Message Clock Out) pin

–2 MSEO (Message Start/End Out) pins

–

EVTO (Event Out) pin



Auxiliary Input Port

–

EVTI (Event In) pin(a)

1.5.28

IEEE 1149.1 (JTAG) controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. All data

input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE standard.

The JTAG controller provides the following features:



IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)



Selectable modes of operation include JTAGC/debug or normal system operation.



A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–

BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD



A 5-bit instruction register that supports the additional following public instructions:

–

ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,

ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,

ACCESS_AUX_TAP_NASPS_1



Three test data registers: a bypass register, a boundary scan register, and a device

identification register.



A TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry.

1.5.29

On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:



Uses external NPN transistor



Regulates external 3.3 V to 5.0 V down to 1.2 V for the core logic



Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

a. At least one TCK clock is necessary for the EVTI signal to be recognized by the MCU.

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