COP425C datasheet(17/24 Pages) NSC

17 / 24 page

Description of Selected Instructions

XAS INSTRUCTION

XAS (Exchange A with SIO) copies C to the SKL latch and

exchanges the accumulator with the 4-bit contents of the

SIO register The contents of SIO will contain serial-inseri-

al-out shift register or binary counter data depending on the

value of the EN register If SIO is selected as a shift register

an XAS instruction can be performed once every 4 instruc-

tion cycles to effect a continuous data stream

LQID INSTRUCTION

LQID (Load Q Indirect) loads the 8-bit Q register with the

contents

ROM

pointed

the

11-bit

word

PC10PC8AM LQID can be used for table lookup or code

conversion such as BCD to seven-segment The LQID in-

struction ‘‘pushes’’ the stack (PCa1

xSAxSBxSC)

and replaces the least significant 8 bits of the PC as follows

xPC(74) RAM(B)xPC(30) leaving PC(10) PC(9)

and PC(8) unchanged The ROM data pointed to by the new

address is fetched and loaded into the Q latches Next the

stack is ‘‘popped’’ (SC

xSBxSAxPC) restoring the

saved value of PC to continue sequential program execu-

tion Since LQID pushes SB

xSC the previous contents

of SC are lost

Note

LQID uses 2 instruction cycles if executed one if skipped

JID INSTRUCTION

JID (Jump Indirect) is an indirect addressing instruction

transferring program control to a new ROM location pointed

to indirectly by A and M It loads the lower 8 bits of the ROM

address register PC with the contents of ROM addressed by

the 11-bit word PC108AM PC10PC9 and PC8 are not

affected by JID

Note

JID uses 2 instruction cycles if executed one if skipped

SKT INSTRUCTION

The SKT (Skip On Timer) instruction tests the state of the T

counter overflow latch (see internal logic above) executing

the next program instruction if the latch is not set If the

latch has been set since the previous test the next program

instruction is skipped and the latch is reset The features

associated with this instruction allow the processor to gen-

erate its own time-base for real-time processing rather than

relying on an external input signal

Note

If the most significant bit of the T counter is a 1 when a CAMT instruc-

tion loads the counter the overflow flag will be set The following

sample of codes should be used when loading the counter

load T counter

CAMT

skip if overflow flag is set and reset it

SKT

NOP

IT INSTRUCTION

The IT (idle till timer) instruction halts the processor and

puts it in an idle state until the time-base counter overflows

This idle state reduces current drain since all logic (except

the oscillator and time base counter) is stopped

INIL INSTRUCTION

INIL (Input IL Latches to A) inputs 2 latches IL3 and IL0

CKO and 0 into A The IL3 and IL0 latches are set if a low-

going pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0

inputs since the last INIL instruction provided the input

pulse stays low for at least two instruction cycles Execution

of an INIL inputs IL3 and IL0 into A3 and A0 respectively

and resets these latches to allow them to respond to subse-

quent low-going pulses on the IN3 and IN0 lines If CKO is

mask programmed as a general purpose input an INIL will

input the state of CKO into A2 If CKO has not been so

programmed a ‘‘1’’ will be placed in A2 A0 is input into A1

IL latches are cleared on reset IL latches are not available

on the COP445C425C and COP426C

INSTRUCTION SET NOTES

a The first word of a program (ROM address 0) must be a

CLRA (Clear A) instruction

b Although skipped instructions are not executed they are

still fetched from the program memory Thus program

paths take the same number of cycles whether instruc-

tions are skipped or executed except for JID and LQID

c The ROM is organized into pages of 64 words each The

Program Counter is a 11-bit binary counter and will count

through page boundaries If a JP JSRP JID or LQID is

the last word of a page it operates as if it were in the next

page For example a JP located in the last word of a

page will jump to a location in the next page Also a JID

or LQID located in the last word of every fourth page (ie

hex address 0FF 1FF 2FF 3FF 4FF etc) will access

data in the next group of four pages

Note

The COP424C425C426C needs only 10 bits to address its ROM

Therefore the eleventh bit (P10) is ignored

Power Dissipation

The lowest power drain is when the clock is stopped As the

frequency increases so does current Current is also lower

at lower operating voltages Therefore the user should run

at the lowest speed and voltage that his application will al-

low The user should take care that all pins swing to full

supply levels to insure that outputs are not loaded down and

that inputs are not at some intermediate level which may

draw current Any input with a slow rise or fall time will draw

additional current A crystal or resonator generated clock

input will draw additional current An RC oscillator will draw

even more current since the input is a slow rising signal

If using an external squarewave oscillator the following

equation can be used to calculate operating current drain

ICOeIQaVc40cFiaVc1400cFiDv

where ICOechip operating current drain in microamps

quiescent leakage current (from curve)

CKI frequency in MegaHertz

chip VCC in volts

divide by option selected

For example at 5 volts VCC and 400 kHz (divide by 4)

ICOe20a5c40c04a5c1400c044

ICOe20a80a700e800 mA

At 24 volts VCC and 30 kHz (divide by 4)

ICOe6a24c40c003a24c1400c0034

ICOe6a288a252e3408 mA

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