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ATSAM9703

1710C–DRMSD–12/02

Reset and

Power-down

During power-up, the RESET input should be held low until the crystal oscillator and

PLL are stabilized, which can take abOut 20 ms. A typical RC/diode power-up network

canbeused.

After the low-to-high transition of RESET, the following occurs:

•

The synthesis enters an idle state.

•

The RUN Output is set to zero.

•

Firmware execution starts from address 0100H in ROM space (WCS0 low).

If PDWN is asserted low, then all I/Os and Outputs will be floated and the crystal oscilla-

tor and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit

power-down, PDWN has to be asserted high, then RESET applied.

Recommended Board

Layout

As for all HCMOS high-integration ICs, some rules of board layout should be followed

for reliable operation:

two 1N4148 diodes in serial. This guarantees a minimum voltage drop of 1.2V.

IC.

•Crystal, LFT

The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-

R and the ATSAM9703 should be short and shielded. The ground return from the com-

pensation capacitors and LFT filter should be the GND plane from ATSAM9703.

•

Analog Section

A specific AGND ground plane should be provided, which connects by a single trace to

the GND ground. No digital signals should cross the AGND plane. Refer to the codec

vendor recommended layOut for correct implementation of the analog section.

•

Unused Inputs

Unused inputs should always be connected. A floating input can cause internal oscilla-

tion inside the IC, which can destroy the device by dramatically increasing the power

consumption. If the power-down feature is to be used, care should be taken that no pin

is left floating during power down. Usually, a 1 M

Ω ground return is sufficient.