A3980KLP datasheet(13/18 Pages) ALLEGRO

13 / 18 page

Automotive DMOS Microstepping Driver

with Translator

A3980

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Mixed Decay Operation. Depending on the step

sequence, if the voltage on the PFD pin is between

0.6

× VDD and 0.21 × VDD, the full-bridge can operate

in mixed decay mode, as shown in ﬁgures 5 through 8.

As the trip point is reached, the A3980 goes into fast

decay mode until the voltage on the RC pin decays to

the same level as the voltage applied to the PFD pin. The

duration of time that the bridge operates in fast decay

mode, tFD (ns), is estimated by

tFD = RT

× CT× ln[0.6 (VDD ⁄ VPFD)]

over a range of values from CT= 470 pF to 1500 pF and

from RT = 12 kΩ to 100 kΩ.

After this fast decay period, the A3980 switches to slow

decay mode for the remainder of the ﬁxed off-time

period.

Synchronous Rectiﬁcation. When a PWM-off

cycle is triggered by an internal ﬁxed-off-time cycle,

load current recirculates according to the decay mode

selected by the control logic. The synchronous rectiﬁca-

tion feature turns on the appropriate FETs during current

decay, and effectively shorts out the body diodes with

the low DMOS RDSON. This reduces power dissipa-

tion signiﬁcantly, and eliminates the need for external

Schottky diodes. Synchronous rectiﬁcation has two

modes: Active mode and Disabled mode (described below).

Active Mode. When the input on the SR terminal

is set at logic low, Active mode is enabled. This mode

allows synchronous rectiﬁcation to occur, but when a

zero current level is detected, it also prevents reversal of

the load current by turning off synchronous rectiﬁcation.

This prevents the motor winding from conducting in the

reverse direction.

Disabled Mode. When the input on the SR terminal

is set at logic high, Disabled mode takes effect. This

mode disables synchronous rectiﬁcation. This mode

is typically used when external diodes are required to

transfer power dissipation from the A3980 package to

the external diodes.

Shutdown. In the event of an overtemperature fault

or an undervoltage fault on VREG, the DMOS outputs

of the A3980 are disabled until the fault condition is

removed. In the case of an overvoltage fault, the sink

DMOS FETs are switched on, and the source FETs off.

At power-up, and in the event of low VDD, the UVLO

circuit disables the DMOS outputs until VDD reaches the

minimum level. Once VDD is above the minimum level,

the translator resets to the Home state and the DMOS

outputs are re-enabled.

Thermal Protection. All drivers are turned off

when the junction temperature reaches the thermal

shutdown value, typically 170

C. This is intended only

to protect the A3980 from failures due to excessive junc-

tion temperatures. Thermal protection will not protect

the A3980 from continuous short circuits, and additional

fault diagnostics are integrated for this purpose. Thermal

shutdown has a hysteresis of approximately 15

C.

Diagnostic Features. The A3980 includes moni-

tor circuits that can detect shorts to VBB, shorts to

ground, and shorted or open circuit load. Short circuits

are detected by monitoring the voltage across the driving

DMOS FETs and the open load is detected by monitor-

ing the phase current when the motor is in the Home

microstep position. All fault detection takes place fol-

lowing a delay after the blank time.

Short to VBB. A short from any of the motor connec-

tions to the battery or VBB connection is detected by

monitoring the voltage across the bottom FETs in each

full-bridge. When the FET is on, the voltage should be

no greater than the VDSLT value deﬁned in the Electrical

Characteristics table.

Short to Ground. A short from any of the motor con-

nections to ground is detected by monitoring the voltage

across the top FETs in each full-bridge. When the FET

is turned on, the voltage should be no greater than the

VDSHT value deﬁned in the Electrical Characteristics

table.

A3980KLP датащи(PDF) 13 Page - Allegro MicroSystems

A3980KLP датащи(HTML) 13 Page - Allegro MicroSystems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

датащи скачать

ссылки URL