XRT71D00

E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER





REV. 1.01

5

11

FSS/(SClk)

I

FIFO Size Select Input/Serial Clock Input.

The function of this depends on whether XRT71D00 is configured in Hard-

ware or Host mode.

Hardware Mode—FIFO Size Select Input

When high: Selects 32 bits FIFO.

When low: Selects 16 bits FIFO.

Host Mode—Microprocessor Serial Interface Clock Signal

This signal will be used to (1) sample the data, on the SDI pin, on the rising

edge of this signal. Additionally, during “Read” operations, the Micropro-

cessor Serial Interface will update the SDO output on the falling edge of

this signal.

12

HOST/HW

I

Host/Hardware Mode Select:

An active-high input enables the Host mode. Data is written to the com-

mand registers to configure the XRT71D00.

In the Host mode, the states of discrete input pins are inactive.

An active-low input enables the Hardware Mode.In this mode, the discrete

inputs are active.

13

NC

***

This pin is not connected internally.

14

FL

O

FIFO Limit.

This output pin is driven high whenever the internal FIFO comes within

two-bits of being completely full.

15

BWS/

Ch_Addr_1

I

Bandwidth Select Input/Channel Addr_1 Assignment Input.

The function of this input pin depends on whether XRT71D00 is configured

in Host or Hardware mode.

Hardware Mode—Bandwidth Select Input:

Connect this pin high to select wide jitter transfer bandwidth, and connect

low to select narrow jitter transfer bandwidth.

Host Mode—Channel_Addr_1 Assignment Input:

This input pin, along with pin 28 permits the user to assign a “Channel

Address” to the XRT71D00 device.

16

NC

***

This pin is not connected internally.

17

NC

***

This pin is not connected internally.

18

DJA/

(SDO)

I/(O)

Disable Jitter Attenuator Input/Serial Data Output pin:

The function of this pin depends on whether XRT71D00 is configured in

Host or Hardware mode.

Hardware Mode—Disable Jitter Attenuator:

An active-high disables the Jitter Attenuator.The RPOS/RNEG and RClk

will be passed through without jitter attenuation.

Host Mode—Serial Data Output:

This pin will serially output the contents of the specified Command Regis-

ter, during “Read” Operations. The data, on this pin, will be updated on the

falling edge of the SClk input signal. This pin will be tri-stated upon com-

pletion of data transfer.

been configured to operate in the “HOST” Mode.

19

RST

I

A high-low transition will re-center the internal FIFO, and will clear the

Command Registers (for Host Mode operation). Resetting this pin may

corrupt data within the device.

For normal operation, pull this pin to VDD.

PIN DESCRIPTION