FT4222HQ-C-R datasheet(18/49 Pages) FTDI

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FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC

1.3

Document No.: FT_001011 Clearance No.: FTDI#405

5.2.4 SPI Timing

Figure 5.5 SPI Timing

The Table5.2 shows the timing information for QuadSPI. The result is under the condition of all the

related pins with 5pF loading. T6 is the required setup time to the related SCK edge for the input data

path of QuadSPI. The minimum value of T4 means that the guaranteed setup time to the related SCK

edge for connected device to fetch data from QuadSPI. The maximum value of T6 means that data can

be accepted correctly by QuadSPI with 5pF pin loading assumed. If the pin load is larger, the timing

should be considered conservatively.

Parameter

Min (ns)

Typ(ns)

Max(ns)

Description

T1@master

T2+T3

SCK Period when QuadSPI as master

T1@slave

Acceptable SCK Period when QuadSPI as slave device

12.5

SCK HIGH, related to the operating clock and ratio

12.5

SCLK LOW, related to the operating clock and ratio

T3-2.0

T3-1.1

Data output path: setup time to corresponding SCK edge

T2+0.1

T2+0.6

Data output path: hold time to corresponding SCK edge

9.8

Data input path: required setup time to corresponding

SCK edge

0.1

Data input path: required hold time to corresponding SCK

edge

6*T1

SSxO setup time to 1st SCK period boundary

6*T1

SSxO hold time from last SCK period boundary

T10@master

6*T1

Idle time on SCK between byte boundary when master

T10@slave

Idle time on SCK between byte boundary when slave

Table 5.2 SPI Timing for VCCIO=3.3V with 5pF output pin load

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