TDA8757 datasheet(21/37 Pages) PHILIPS

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Philips Semiconductors

TDA8757

Triple 8-bit ADC 170 Msps

Preliminary data

Rev. 07 — 28 February 2002

21 of 37

9397 750 09457

The default programmed value is as follows:

• No external clock: bit ‘Ckext’ is logic 0

• Phase shift for CKDATA is 0 degrees.

9.1.8

DEMUX register

The default programming is:

• Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1

• CKREFO with positive polarity: bit ‘Ckrp’ = 0

• CKDATA not reversed: bit ‘Ckdp’ = 0

• CKDATA not delayed: bit ‘Ckdd’ = 0

• De-multiplexed outputs: bit ‘Dmx’ = 1

• Interleaved outputs: bit ‘Shift’ = 1

• Odd pixels on port A: bit ‘Odda’ = 1.

9.1.9

Power-down mode

• When the supply is completely switched off, the registers are set to their default

values; in that event they have to be reprogrammed if the required settings are

different (e.g. through an EEPROM)

• When the device is in Power-down mode (pin PD = HIGH), the previously

programmed register values remain unaffected.

9.2 I2C-bus protocol

The address of the circuit for the I2C-bus is 1001 1XX0.

Bits ‘A1’ and ‘A0’ are ﬁxed by the potential on pins A2 and A1. Bit ‘RW’ must always

be equal to logic 0 because it is not possible to read the data in the register. The

timing and protocol for the I2C-bus are standard. Two sequences are available;

see Table 13 and 14.

Table 11: Phase registers bits

Phase shift (deg)

000000

00001

11.25

...

11110

337.5

11111

348.75

Table 12: Register format

10011A2

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