SSD1828Z datasheet(13/43 Pages) ETC

13 / 43 page

SSD1828

Rev 1.10

07/2002

SOLOMON

PIN DESCRIPTION

6.1

RES

This pin is reset signal input. When the pin is low, initialization of the chip is executed.

6.2

PS0

This pin pair with PS1 to determine the interface protocol between the driver and MCU. Refer to

PS1 pin descriptions for more details.

6.3

PS1

This pin pair with PS0 to determine the interface protocol between the driver and MCU,

according to the following table.

Table 3 - PS0 & PS1 Interface

PS0

PS1

Interface

3-wire SPI (write only)

4-wire SPI (write only)

8080 parallel interface (read and write allowed)

6800 parallel interface (read and write allowed)

6.4

CS#

This pin is chip select input. The chip is enabled for display data/command transfer only when

CS is low.

6.5

D/C

This input pin is to identify display data/command cycle. When the pin is high, the data written to

the driver will be written into display RAM. When the pin is low, the data will be interpreted as

command. This pin must be connected to VSS when 3-lines SPI interface is used. .

6.6

R/W(WR#)

This pin is microprocessor interface signal. When interfacing to a 6800-series microprocessor,

the signal indicates read mode when high and write mode when low. When interfacing to an

8080-microprocessor, a data write operation is initiated when R/W(WR) is low and the chip is

selected.

6.7

E(RD#)

This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor,

a data operation is initiated when E(RD) is high and the chip is selected. When interfacing to an

8080-microprocessor, a data read operation is initiated when E(RD) is low and the chip is

selected.

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