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LP3961 датащи(PDF) 12 Page - National Semiconductor (TI) |
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LP3961 датащи(HTML) 12 Page - National Semiconductor (TI) |
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12 / 20 page ![]() Applications Information (Continued) Sense Pin In applications where the regulator output is not very close to the load, LP3964 can provide better remote load regulation using the SENSE pin. Figure 2 depicts the advantage of the SENSE option. LP3961 regulates the voltage at the output pin. Hence, the voltage at the remote load will be the regula- tor output voltage minus the drop across the trace resis- tance. For example, in the case of a 3.3V output, if the trace resistance is 100m Ω, the voltage at the remote load will be 3.22V with 800mAmps of load current, I LOAD. The LP3964 regulates the voltage at the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in Figure 2. If the sense option pin is not re- quired, the sense pin must be connected to the V OUT pin. Shutdown Operation A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively terminated through a 10k Ω pull-up resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. DS101129-7 FIGURE 1. Error Flag Operation DS101129-8 FIGURE 2. Improving remote load regulation using LP3964 www.national.com 12 |
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