TLK1521

500 Mbps to 1.3 Gbps TRANSCEIVER

SLLS591A− OCTOBER 2003 − REVISED JANUARY 2004

8

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

SIGNAL PIN

DOUTTXP

60

Output

(High-Z

Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to

copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK

DOUTTXN

59

(High-Z

power up)

copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK

value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are

active when LOOPEN is low. During power-on reset, these pins are high impedance.

DINRXP

54

Input

Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a

copper or an optical I/F module.

DINRXN

53

Input

Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a

copper or an optical I/F module.

GTX_CLK

8

Input

Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter

interface TXD. The frequency range of GTX_CLK is 25 MHz to 65 MHz. The transmitter uses the rising

edge of this clock to register the 18-bit input data (TXD) for serialization.

TXD0

62

TXD1

63

TXD2

64

TXD3

2

TXD4

3

TXD5

4

TXD6

6

TXD7

7

Transmit data bus. These inputs carry the 18-bit parallel data output from a protocol device to the

TXD8

10

Input

Transmit data bus. These inputs carry the 18-bit parallel data output from a protocol device to the

transceiver for encoding, serialization and transmission. This 18-bit parallel data is clocked into the

TXD9

11

Input

transceiver for encoding, serialization and transmission. This 18-bit parallel data is clocked into the

transceiver on the rising edge of GTX_CLK as shown in Figure 6.

TXD1

12

transceiver on the rising edge of GTX_CLK as shown in Figure 6.

TXD11

14

TXD12

15

TXD13

16

TXD14

17

TXD15

19

TXD16

20

TXD17

22

RXD0

51

RXD1

50

RXD2

49

RXD3

47

RXD4

46

RXD5

45

RXD6

44

RXD7

42

Output

Receive data bus. These outputs carry 18-bit parallel data output from the transceiver to the protocol

RXD8

40

Output

(High-Z on

Receive data bus. These outputs carry 18-bit parallel data output from the transceiver to the protocol

device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 7.

RXD9

39

(High-Z on

power up)

device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 7.

These pins are tri-stated during power-on reset.

RXD10

37

power up)

These pins are tri-stated during power-on reset.

RXD11

36

RXD12

35

RXD13

34

RXD14

32

RXD15

31

RXD16

30

RXD17

29

RX_CLK

41

Output (low

on power up)

Recovered clock. Output clock that is synchronized to RXD. RX_CLK is the recovered serial data rate

clock divided by 20. RX_CLK is held low during power-on reset.