MPT57481

240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS

SGLS099 – MARCH 1997

3

POST OFFICE BOX 655303

detailed description

acquisition of line data

Acquisition of line data begins when a start pulse is applied to the EIO1 or EIO2 input terminal and is complete

when all 240 channels of the Input Register have been loaded with new RGB data. When the first clock pulse,

CLK0, is applied while the EIO terminal is biased high by the start pulse, an enable pulse enters the Shift

Register and RGB data enters the Data Latch on the clock’s rising edge. The enable pulse, after entering the

Shift Register, positions itself to address the Input Register for loading of RGB data from the Data Latch on the

rising edge of succeeding clock pulses after CLK0.

With each succeeding clock pulse, CLK (1 – 80), the Input Register is repeatedly addressed by the Shift Register

and updated with new RGB data. One of 80 parallel outputs of the Shift Register addresses the Input Register

with each transition of the clock pulse. Each output addresses three separate but adjacent channels of the Input

Register simultaneously in a ascending or descending order between channels (1..240) as the enable pulse

advances to the right or left from one output to the next. Channels (3n–2, 3n–1, and 3n ) are addressed on

the rising edge of CLKn by each output where ‘n’ is the number of clock pulse and addressing output.

While channels (3n–2, 3n–1, and 3n) are being addressed by the Shift Register outputs, 18-bit (6 bit

× 3) RGB

data stored in the Data Latch is loaded into the channels that are enabled. RGB data, originating at three 6-bit

data input terminals, D05..D00, D15..D10, and D25..D20, is routed through the 18-bit Data Latch to the input

of channels (3n–2, 3n–1, and 3n), respectively. New RGB data can be entered at the data input terminals and

routed to the Input Register with each transition of the clock pulse from 1 to 80. After CLK(80), all 240 channels

of the Input Register are addressed and loaded completing the acquisition of RGB line data.

cascading drivers

If the pixels of a LCD display are greater than what one MPT57481 can drive, additional drivers can be cascaded

together to extend the RGB line data by connecting the EIO output terminals of one driver to the EIO input

terminals of the next driver. Between the rising edges of clock pulse, CLK( d80–1 and d80: d = number of driver),

the enable pulse exits the Shift Register of one driver at the EIO output terminal and enters at the EIO input

terminal of the next driver. When the enable pulse exits a driver, the driver enters a low-power standby mode

while the next driver is set up to receive new RGB input data. The driver in standby mode goes back into normal

mode when the next enable start pulse enters at its EIO input terminal.

transfer of line data

RGB line data is transferred from the Input Register to subpixel outputs, OUT (1..240) by a sequence of

transitions of the TP1 and TP2 inputs. TP1 and TP2 are biased high while data is being acquired. After line

data is acquired, data is transferred to the Storage Register and enters each DAC on the rising edge of the last

clock pulse, CLK(d80+1; d = number of last driver) after TP1 transitions to low while TP2 remains high. Transfer

of data beyond the Storage Register is independent of the clock. When TP1 or TP2 are low, each DAC is

precharging period, line data from the Storage Register, already inside each DAC, is converted to analog

voltages during the second and third sequence when TP2 transitions to low with TP1 remaining low, and then

when TP1 transitions back to high with TP2 remaining low. After TP1 goes high, line data, now represented as

analog voltages, transfers to the output of each DAC. The last sequence, when TP2 goes back to high while

TP1 remains high, the precharging period ends and all of the DACs are enabled allowing the analog voltages

to transfer to the subpixel outputs.

64 gray scale subpixel outputs

All 240 outputs of the MPT57481 are driven by separate 6-bit DACs. The output voltage of each DAC, 64 gray

scale, is determined by the reference voltages GMA(0..9) and WB(0,1, or 2) selected by a 6-bit data input and

by the VOP bias voltage. GMA (0..9) gamma correction voltages, WB(0..2) RGB Shift voltages , and VOP