PROGRAMMABLE DIVIDER (N COUNTER)

Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control

Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch

(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data

format is shown below.

7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)

Divide

N

7

N

6

N

5

N

4

N

3

N

2

N

1

Ratio

A

0

0000000

1

0000001

•

•••••••

127

1111111

Notes:

Divide ratio: 0 to 127

B

≥ A

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)

Divide

N

18

N

17

N

16

N

15

N

14

N

13

N

12

N

11

N

10

N

9

N

8

Ratio

B

3

00000000011

4

00000000100

•

•••••••••••

2047

11111111111

Note:

Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)

B

≥ A

PULSE SWALLOW FUNCTION

f

f

Output frequency of external voltage controlled oscillator (VCO)

B:

Preset divide ratio of binary 11-bit programmable counter (3 to 2047)

A:

Preset divide ratio of binary 7-bit swallow counter

(0

≤ A ≤ P; A ≤ B)

f

Output frequency of the external reference frequency oscillator

R:

Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)

P:

Preset modulus of dual moduIus prescaler (P = 64 or 128)

PROGRAMMABLE MODES

Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump tristate

and the output of the F

modes are shown in

Table 1. Truth table for the programmable modes and F

DS012807-7

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