PCI7621 datasheet(95/298 Pages) TI

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4−5

Table 4−3. Command Register Description (continued)

BIT

SIGNAL

TYPE

FUNCTION

MEM_EN

Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles

in PCI memory space.

0 = Disables the PCI7x21/PCI7x11 response to memory space accesses (default)

1 = Enables the PCI7x21/PCI7x11 response to memory space accesses

IO_EN

I/O space control. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI

I/O space.

0 = Disables the PCI7x21/PCI7x11 controller from responding to I/O space accesses (default)

1 = Enables the PCI7x21/PCI7x11 controller to respond to I/O space accesses

4.5

Status Register

The status register provides device information to the host system. Bits in this register can be read normally. A bit

in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit

functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown

through each function. See Table 4−4 for a complete description of the register contents.

Bit

Name

Status

Type

Default

Status

Offset:

06h (Functions 0, 1)

Type:

Read-only, Read/Write

Default:

0210h

Table 4−4. Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

15 ‡

PAR_ERR

Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.

Write a 1 to clear this bit.

14 ‡

SYS_ERR

Signaled system error. This bit is set when SERR is enabled and the PCI7x21/PCI7x11 controller signaled

a system error to the host. Write a 1 to clear this bit.

13 ‡

MABORT

Received master abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI

bus has been terminated by a master abort. Write a 1 to clear this bit.

12 ‡

TABT_REC

Received target abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI

bus was terminated by a target abort. Write a 1 to clear this bit.

11 ‡

TABT_SIG

Signaled target abort. This bit is set by the PCI7x21/PCI7x11 controller when it terminates a transaction on

the PCI bus with a target abort. Write a 1 to clear this bit.

10−9

PCI_SPEED

DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the

PCI7x21/PCI7x11 controller asserts this signal at a medium speed on nonconfiguration cycle accesses.

8 ‡

DATAPAR

Data parity error detected. Write a 1 to clear this bit.

0 = The conditions for setting this bit have not been met.

1 = A data parity error occurred and the following conditions were met:

a. PERR was asserted by any PCI device including the PCI7x21/PCI7x11 controller.

b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.

c. The parity error response bit is set in the command register.

FBB_CAP

Fast back-to-back capable. The PCI7x21/PCI7x11 controller cannot accept fast back-to-back transactions;

thus, this bit is hardwired to 0.

UDF

UDF supported. The PCI7x21/PCI7x11 controller does not support user-definable features; therefore, this

bit is hardwired to 0.

66MHZ

66-MHz capable. The PCI7x21/PCI7x11 controller operates at a maximum PCLK frequency of 33 MHz;

therefore, this bit is hardwired to 0.

‡ This bit is cleared only by the assertion of GRST.

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