CS5540

DS503PP1

15

The filter is optimized to yield better than 80 dB re-

jection between 47 Hz to 63 Hz (i.e. 80 dB mini-

mum rejection for both 50 Hz and 60 Hz) when the

master clock is 32.768 kHz. The filter’s output

word rate can be increased by approximately 1.22X

by using a 40 kHz master clock, although the 50/60

Hz rejection will be sacrificed. The filter has a re-

sponse as shown in Figure 11.

Note:

The converter’s digital filter linearly scales

with MCLK.

D31

D30

D29

D28

D27

D26

D25

D24

01

1

1

1

CH

OD

OF

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

MSB

22212019

18

17

16

15

14

13

12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

11

10

98

76

5

4

3

2

1

LSB

Table 1. Output Conversion Data Register Description (24 bits + flags)

Note:

Plus or minus VFS is defined as a differential input signal equal in magnitude to the voltage between the

VREF+ and VREF- pins. See the text about error flags for overrange and underrange conditions.

Bipolar Input Voltage

Two’s

Complement

>(VFS-1.5 LSB)

7FFFFF

VFS-1.5 LSB

7FFFFF

-----

7FFFFE

-0.5 LSB

000000

-----

FFFFFF

-VFS+0.5 LSB

800001

-----

800000

<(-VFS+0.5 LSB)

800000

Table 2. CS5540 24-Bit Bipolar Output Coding

-140

-120

-100

-80

-60

-40

-20

0

0

20

40

60

80

100

120

Frequency (Hz)

47 Hz

63 Hz

Figure 11. Filter Response (MCLK = 32.768 kHz)