CD54AC74, CD74AC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002

2

POST OFFICE BOX 655303

logic diagram, each flip-flop (positive logic)

TG

C

C

TG

C

C

TG

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

C

– 0.5 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

80

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M package

86

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

– 65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.