REV. 0

–8–

AD9821

IMAGER MODE AND AUX MODE TIMING

DATACLK

OUTPUT

DATA

VIN+

N

N+1

N+2

N+8

N+9

N–10

N–9

N–8

N–1

N

VIN–

NOTES:

1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT DATACLK RISING EDGES (CAN BE INVERTED USING THE CONTROL REGISTER).

2. INTERNAL SAMPLING DELAY (APERTURE)

3. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

Figure 5. Imager Mode Timing

IMAGER

SIGNAL

EFFECTIVE PIXELS

CLPOB

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

EFFECTIVE PIXELS

PBLK

NOTES:

1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

EFFECTIVE DATA

Figure 6. Typical Imager Mode Line Clamp Timing