WM8772 datasheet(62/70 Pages) WOLFSON

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WM8772EFT – 32 PIN TQFP

Production Data

PD Rev 4.1 October 2004

MASTER MODE ADCLRC FREQUENCY SELECT

In Master mode the WM8772EFT generates ADCLRC and ADCBCLK. These clocks are derived

from the master clock and the ratio of ADCMCLK to ADCLRC is set by ADCRATE.

BIT

LABEL

DEFAULT

DESCRIPTION

0001011

ADCLRC and ADCBCLK

Frequency Select

7:5

ADCRATE [2:0]

010

Master Mode

ADCMCLK:ADCLRC Ratio

Select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADC OVERSAMPLING RATE SELECT

For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the

ADC signal processing oversample rate to 64fs. The 64fs oversampling rate is only available in

modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a

128fs oversampling rate irrespective of what this bit is set to.

BIT

LABEL

DEFAULT

DESCRIPTION

0001011

ADC Oversampling Rate

ADCOSR

ADC Oversampling Rate Select

0: 128x oversampling

1: 64x oversampling

ADC HIGHPASS FILTER DISABLE

The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled

using software control bit ADCHPD.

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

ADC Control

ADCHPD

ADC Highpass Filter Disable:

0: Highpass filter enabled

1: Highpass filter disabled

In left justified, right justified or I

2S modes, the ADCLRP register bit controls the polarity of ADCLRC.

If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 23,

Figure 24 and Figure 25. Note that if this feature is used as a means of swapping the left and right

channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register bit is

used to select between early and late modes.

BIT

LABEL

DEFAULT

DESCRIPTION

In Left/Right/I

2S Modes:

ADCLRC Polarity (normal)

0: normal DACLRC polarity

1: inverted DACLRC polarity

0001100

Interface Control

ADCLRP

In DSP Mode:

0: Early DSP mode

1: Late DSP mode

By default, DACLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally

change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of

ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the

polarity of ADCBCLK to the inverse of that shown in Figure 23, Figure 24, Figure 25, Figure 26,

Figure 27, Figure 28 and Figure 29.

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