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SIP32408 датащи(PDF) 9 Page - Vishay Siliconix |
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SIP32408 датащи(HTML) 9 Page - Vishay Siliconix |
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9 / 14 page ![]() SiP32408, SiP32409 Vishay Siliconix Document Number: 63717 S13-0971-Rev. F, 06-May-13 www.vishay.com 9 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com DETAILED DESCRIPTION SiP32408 and SiP32409 are advanced slew rate controlled high side load switches consisted of a n-channel power switch. When the device is enable the gate of the power switch is turned on at a controlled rate to avoid excessive in- rush current. Once fully on the gate to source voltage of the power switch is biased at a constant level. The design gives a flat on resistance throughout the operating voltages. When the device is off, the reverse blocking circuitry prevents current from flowing back to input if output is raised higher than input. The reverse blocking mechanism also works in case of no input applied. APPLICATION INFORMATION Input Capacitor SiP32408 and SiP32409 do not require an input capacitor. To limit the voltage drop on the input supply caused by transient inrush currents, an input bypass capacitor is recommended. A 2.2 µF ceramic capacitor placed as close to the VIN and GND should be enough. Higher values capacitor can help to further reduce the voltage drop. Ceramic capacitors are recommended for their ability to withstand input current surge from low impedance sources such as batteries in portable devices. Output Capacitor While these devices works without an output capacitor, an 0.1 µF or larger capacitor across VOUT and GND is recommended to accommodate load transient condition. It also help to prevent parasitic inductance forces VOUT below GND when switching off. Output capacitor has minimal affect on device’s turn on slew rate time. There is no requirement on capacitor type and its ESR. Enable The EN pin is compatible with both TTL and CMOS logic voltage levels. Enable pin voltage can be above IN once it is within the absolute maximum rating range. For output voltage slew rate control, EN is required to have at least 50 µs delay after the input voltage get ready to enable the device. Protection Against Reverse Voltage Condition SiP32408 and SiP32409 contain a reverse blocking circuitry to protect the current from going to the input from the output in case where the output voltage is higher than the input voltage when the main switch is off. Reverse blocking works for input voltage as low as 0 V. Thermal Considerations SiP32408 and SiP32409 are designed to maintain a constant output load current. Due to physical limitations of the layout and assembly of the device the maximum switch current is 3.5 A, as stated in the Absolute Maximum Ratings table. However, another limiting characteristic for the safe operating load current is the thermal power dissipation of the package. To obtain the highest power dissipation (and a thermal resistance of 170 °C/W) the power pad of the device should be connected to a heat sink on the printed circuit board. Figure 21 shows a typical PCB layout. All copper traces and vias for the IN and OUT pins should be sized adequately to carry the maximum continuous current. The maximum power dissipation in any application is dependant on the maximum junction temperature, TJ(max.) = 125 °C, the junction-to-ambient thermal resistance for the TDFN4 1.2 mm x 1.6 mm package, J-A = 170 °C/W, and the ambient temperature, TA, which may be formulaically expressed as: Figure 27 - Typical Turn-on Delay, Rise Time COUT = 200 µF, CIN = 4.7 µF, ROUT = 10 EN 5VOUT IOUTfor5VOUT 3.6VOUT IOUTfor3.6VOUT 1.5VOUT IOUTfor1.5VOUT 2 V/Div, 0.25 A/Div, 2 ms/Div Figure 28 - Typical Fall Time COUT = 200 µF, CIN = 4.7 µF, ROUT = 10 EN 5VOUT IOUTfor5VOUT 3.6VOUT IOUTfor3.6VOUT 1.5VOUT IOUTfor1.5VOUT 2 V/Div, 0.25 A/Div, 2 ms/Div 170 125 (max.) (max.) A A J A J T T T P - = - = - θ |
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