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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DS21352 датащи(PDF) 63 Page - Dallas Semiconductor |
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DS21352 датащи(HTML) 63 Page - Dallas Semiconductor |
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63 / 137 page  DS21352/DS21552 63 of 137 RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (ADDRESS=1B TO 1D Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RCC1 (1B) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RCC2 (1C) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RCC3 (1D) SYMBOL POSITION NAME AND DESCRIPTION CH24 RCC3.7 Receive Channel 24 Code Insertion Control Bit 0 = do not insert data from the RC24 register into the receive data stream 1 = insert data from the RC24 register into the receive data stream CH1 RCC1.0 Receive Channel 1 Code Insertion Control Bit 0 = do not insert data from the RC1 register into the receive data stream 1 = insert data from the RC1 register into the receive data stream 12. PER–CHANNEL LOOPBACK The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the TIRs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. 13. CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a UART or LAPD controller in Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section 21 for an example. RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS (Address=6C to 6E Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RCBR1 (6C) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RCBR2 (6D) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RCBR3 (6E) SYMBOLS POSITIONS NAME AND DESCRIPTION CH1-24 RCBR1.0-3.7 Receive Channel Blocking Control Bits. 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=32 to 34 Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TCBR1 (32) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TCBR2 (33) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TCBR3 (34) SYMBOLS POSITIONS NAME AND DESCRIPTION CH1-24 TCBR1.0-3.7 Transmit Channel Blocking Control Bits. |
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