DS1961S

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(TA1 and TA2), the DS1961S clears the EN_LFS flag. The lower five bits of the target address TA1 are

ignored because only the page number is relevant. If the target address as sent by the master is valid (i.e.,

in the range of 0000h and 007Fh), and the secret is not write-protected, the SHA engine starts. The master

AAh if the copy was successful, but does not modify the scratchpad if the SHA engine did not start

because of an incorrect address or because of write protection. The master should read at least one byte at

the conclusion of the copy delay. Reading AAh indicates that the copy was successful. Reading FFh

indicates that the copy was not successful because of an incorrect address or because of write protection.

Since the content of the scratchpad is used as a partial secret, the master must fill the scratchpad with a

known 8-byte data pattern using the write scratchpad command before it issues the compute next secret

command. Otherwise the new secret depends on data that was unintentionally left in the scratchpad from

previous commands.

Copy Scratchpad [55h]

The data memory of the DS1961S can be read without any restrictions. Executing the copy scratchpad

command to write new data to the memory or register page, however, requires the knowledge of the

device’s secret and the ability to perform an SHA-1 computation to generate the 160-bit MAC to start the

data transfer from the scratchpad to the memory. The master can perform the MAC computation in

software or use a DS1963S as a coprocessor. The coprocessor approach has the benefit that the secret

remains hidden in the coprocessor iButton. The sequence in which the resulting MAC needs to be sent to

the DS1961S is shown in Table 2. Tables 3A and 3B show how the various data components are entered

into the SHA engine. The SHA computation algorithm is explained later in this document.

Table 2. MESSAGE AUTHENTICATION CODE TRANSMISSION SEQUENCE

E[31:24]

E[23:16]

E[15:8]

E[7:0]

D[31:24]

D[23:16]

D[15:8]

D[7:0]

C[31:24]

C[23:16]

C[15:8]

C[7:0]

B[31:24]

B[23:16]

B[15:8]

B[7:0]

A[31:24]

A[23:16]

A[15:8]

A[7:0]

The transmission is least significant bit first starting with register E.

After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern,

which should have been obtained by an immediately preceding read scratchpad command. This 3-byte

pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that

order). If the authorization code matches and the target memory is not write-protected, the DS1961S

starts its SHA engine to compute a 160-bit MAC that is based on the current secret, all of the scratchpad

data, the first 28 bytes of the addressed memory page, and the first seven bytes of the identity register (the

the voltage on the 1-Wire line must not drop below 2.8V. Simultaneously the master computes a MAC

Shift

Direction