DS1868 datasheet(3/14 Pages) DALLAS

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DS1868

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DS1868 BLOCK DIAGRAM Figure 1

I/O SHIFT REGISTER Figure 2

Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper

position value and lastly the potentiometer-0 wiper position value.

When wiper position data is to be written to the DS1868, 17 bits (or some integer multiple) of data should

always be transmitted. Transactions which do not send a complete 17 bits (or multiple) will leave the

After a communication transaction has been completed the RST signal input should be taken to a low

state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state,

the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.

A new wiper position will only engage after a RST transition to the inactive state. On device power-up,

wiper position will be random.

STACKED CONFIGURATION

The potentiometers of the DS1868 can be connected in series as shown in Figure 3. This is referred to as

the stacked configuration and allows the user to double the total end-to-end resistance of the part. The

resolution of the combined potentiometers will remain the same as a single potentiometer but with a total

of 512 wiper positions available. Device resolution is defined as RTOT /256 (per potentiometer); where

RTOT equals the total potentiometer resistance.

The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the

multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer

wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O

shift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the

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