CS7410

DS553PP1

31

4.4

SDRAM / DRAM Interface

These pins are used to interface the CS7410 with external synchronous or EDO DRAMs. Data widths of 4

to 16 bits are supported. The CS7410 supports word or block transfers (partial word transfers are not re-

gives pin definitions for interfacing to EDO DRAM.

68

SER2_CS

B

Chip select for 4-wire serial port (output if master, input if

slave mode). Can also be used as bidirectional ready line.

69

SER3_CLK

O

Clock output

70

SER3_DO

O

Data output – up to 32 bits per transfer.

72

SER3_DI

I

Data input – up to 96 bits per transfer.

74

SER3_SS0

O

Slave select for first peripheral (programmable polarity)

76

SER3_SS1

O

Slave select for second peripheral (programmable polar-

ity)

Table 9. Serial Interface Pins (Continued)

Pin

Signal Name

Type

Description

3, 4, 5, 6, 7, 8, 9,

10, 11, 13, 15, 20,

21, 22, 23, 24

DRAM

Data[15..0]

B

Memory Data Bus.

25, 26, 27, 28,

29, 30, 31, 32,

33, 34, 35, 36

DRAM

Address[11..0]

O

Memory Address Bus. Connect in order starting with

DR_Addr[0] to all RAM address pins not already connected

to DR_BS_L or DR_AP.

37

DR_RAS_L

O

Memory Row Address Strobe

39

DR_CAS_L

O

Memory Column Address Strobe

41

M_WE_L

O

Memory Write Enable

43

DR_CKO

O

SDRAM Clock

45

DR_CKE

O

SDRAM Clock Enable

46

DR_BS_L

O

Bank Selection. Always connect to RAM BS or BS0 pin.

47

M_AP_OE

O

Memory Auto Pre-charge. Always connect to RAM AP pin.

Table 10. SDRAM Interface

Pin

Signal Name

Type

Description

3, 4, 5, 6,

7, 8,

9, 10,

11, 13,

15, 20, 21, 22,

23, 24

DRAM

Data[15..0]

B

Memory Data Bus.

Table 11. EDO DRAM Interface