LM9811 datasheet(21/36 Pages) NSC

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Block Diagram of LM9811-Based System

Applications Information

1.0 THEORY OF OPERATION

The LM9811 removes errors from and digitizes a linear CCD

pixel stream, while providing all the necessary clock signals

to drive the CCD. Offset and gain errors for individual pixels

are removed at the pixel rate. Offset errors are removed

through correlated double sampling (CDS). Gain errors

(which may come from any combination of PRNU, uneven il-

lumination, cos

4 effect, RGB filter mismatch, etc.) are re-

moved through the use of a 8-bit programmable gain ampli-

fier (PGA) in front of the ADC.

1.1 The Analog Signal Path

(See Block Diagram)

The analog output signal from the CCD is connected to the

OS Input of the LM9811 through a 0.01 µF (typical, see Sec-

tion 4.2,

Clamp Capacitor Selection ) DC blocking capacitor.

During the CCD’s optical black pixel segment at the begin-

ning of every line, this input is clamped to the REF OUT

MID

voltage (approximately 2.45V). This DC restore operation

fixes the reference level of the CCD pixel stream at REF

OUT

MID.

The signal is then buffered and fed to a digitally-programmed

4-bit VGA (variable gain amplifier). The gain of the VGA is

digitally programmable in 16 steps from 1V/V to 3V/V. The

VGA is used to compensate for peak white CCD outputs less

than the 1.225V full-scale required by the LM9811 for maxi-

mum dynamic range. When used with parallel output CCDs,

the VGA can fine-tune the amplitude of the red, green, and

blue signals. For a detailed explanation of the VGA, see Sec-

tion 4.3.

The output of the VGA goes into the CDS (Correlated Double

Sampling) stage, consisting of two sample/hold amplifiers:

S/H Ref (Reference) and S/H Signal. The reference level of

the signal is sampled and held by the S/H Ref circuit and the

active pixel data is sampled and held by the S/H Signal cir-

cuit. The output of S/H Ref is subtracted from the S/H Signal

output and amplified by 2. The full-scale signal range at this

point is approximately 2.45Vp-p. CDS reduces or eliminates

many sources of noise, including reset noise, flicker noise,

and both high and low frequency pixel-to-pixel offset varia-

tion. For more information on the CDS stage, see Section

4.4.

At this point an offset voltage can be injected by the 5-bit (4

bits + sign) Offset DAC. This voltage is designed to compen-

sate for any small fixed DC offset introduced by the CDS

S/Hs and the x2 amplifier. The LSB size of the DAC is ap-

proximately 1.7 ADC LSBs (4 mV). The adjustment range is

±25 ADC LSBs. For a detailed explanation of the Offset

DAC, see Section 4.6.

The next stage is the PGA. This is a programmable gain am-

plifier that changes the gain

at the pixel rate to correct for

gain errors due to PRNU, uneven illumination (such as cos

effect), RGB filter mismatch, etc. The gain adjustment range

is 0 dB to 9 dB (1V/V to 3V/V) with 8 bits of resolution. The

gain data (correction coefficients) is provided on the

CD0–CD7 bus. The gain may also be fixed at any value be-

tween 0 dB and 9 dB with the PGA Gain Coefficient con-

figuration register. For additional information on the PGA,

see Section 4.7.

An approximately 8 LSB (19 mV) offset can be added at the

output of the PGA stage if necessary to ensure that the offset

is greater than zero. This eliminates the possibility of a nega-

tive offset clipping the darkest output pixels. For more infor-

mation on the Offset Add Bit, see Section 4.8.

Finally, the output of the PGA is digitized by the ADC and

made available on the DD0–DD9 bus (Section 4.9).

Three reference voltages are used throughout the signal

path: the externally supplied REF IN (1.225V), and the inter-

nally generated REF OUT

MID

(2.45V) and REF OUT

(3.675V).

DS012813-28

Power supplies and bypass capacitors not shown for clarity.

FIGURE 20. LM9811 System Block Diagram

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