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LTC2901-1IGN датащи(PDF) 12 Page - Linear Technology |
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LTC2901-1IGN датащи(HTML) 12 Page - Linear Technology |
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12 / 16 page ![]() 12 LTC2901 2901is sn2901 Pull-Up Current vs V2 curve). Output rise time (10% to 90%) is estimated using: tRISE ≈ 2.2 • RPU • CLOAD where RPU is the on-resistance of the pull-up transistor. The on-resistance as a function of the V2 voltage at room temperature is estimated using: R V PU =Ω 610 21 5 • – with V2 = 3.3V, RPU is about 260k. Using 150pF for load capacitance, the rise time is 86 µs. If the output needs to pull up faster and/or to a higher voltage, a smaller external pull-up resistor may be used. Using a 10k pull- up resistor, the rise time is reduced to 3.3 µs for a 150pF load capacitance. The LTC2901-2 has an active pull-up to V2 on the RST output. The typical performance curve (RST Pull-Up Cur- rent vs V2 curve) demonstrates that the pull-up current is somewhat linear versus the V2 voltage and RPU is esti- mated to be approximately 625 Ω. A 150pF load capaci- tance makes the rise time about 206ns. Watchdog Timer The watchdog circuit typically monitors a µP’sactivity.The µP is required to change the logic state of the WDI pin on a periodic basis in order to clear the watchdog timer and prevent the WDO pin from going low. Whenever RST is low, the watchdog timer is cleared and WDO is set high. The watchdog timer is started when RST pulls high. Subsequent edges received on the WDI pin will clear the watchdog timer. The timer will continue to run until the watchdog timer times out. Once the watchdog timer times out, internal circuitry will bring the WDO pin low. WDO will remain low and the watchdog timer will remain cleared until the next edge is received on the WDI pin or until RST goes low. To disable the watchdog timer, simply ground the CWT pin (Pin 9). With CWT held at ground, any reset event will force WDO high indefinitely. It is safe to leave the WDI pin (Pin 8) unconnected because the weak internal pull-up (10 µA typ) will pull WDI high. Tying WDI to V1 or ground is also allowed, but grounding the WDI pin will force the pull-up current to be drawn continuously. Selecting the Reset Timing Capacitor The reset time-out period is adjustable in order to accom- modate a variety of microprocessor applications. The reset time-out period, tRST, is adjusted by connecting a capacitor, CRT, between the CRT pin and ground. The value of this capacitor is determined by: CRT = tRST • 217.4 • 10–9 with CRT in Farads and tRST in seconds. The CRT value per millisecond of delay can also be expressed as CRT/ms = 217.4 (pF/ms). Leaving the CRT pin unconnected will generate a mini- mum reset time-out of approximately 50 µs. Maximum reset time-out is limited by the largest available low leakage capacitor. The accuracy of the time-out period will be affected by capacitor leakage (the nominal charging current is 2 µA) and capacitor tolerance. A low leakage ceramic capacitor is recommended. Selecting the Watchdog Timing Capacitor The watchdog time-out period is adjustable and can be optimized for software execution. The watchdog time-out period, tWD, is adjusted by connecting a capacitor, CWT, between the CWT pin and ground. Given a specified watchdog time-out period, the capacitor is determined by: CWT = tWD • 50 • 10–9 with CWT in Farads and tWD in seconds. The CWT value per millisecond of delay can also be expressed as CWT/ms = 50 (pF/ms). Leaving the CWT pin unconnected will generate a mini- mum watchdog time-out of approximately 200 µs. Maxi- mum time-out is limited by the largest available low leakage capacitor. The accuracy of the time-out period will be affected by capacitor leakage (the nominal charging current is 2 µA) and capacitor tolerance. A low leakage ceramic capacitor is recommended. Monitoring Power Supply Controller Activity Figure 7 demonstrates how the LTC2901 can be used to monitor switcher activity. The monitor is configured to supervise 3.3V, 2.5V, 1.8V and one adjustable input. APPLICATIO S I FOR ATIO |
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