Pin Description

PIN

NAME

DESCRIPTION

APPLICATION INFORMATION

1V

IN

System high potential input.

The diode “OR” of several lines entering the PD, it is the more

positive input potential.

2

RSIG

Signature resistor pin.

Connect a 25k

Ω signature resistor from V

detection.

3

RCLASS

Classification resistor pin.

Connect the classification programming resistor from this pin to

V

4

UVLO

Line under-voltage lockout.

An external resistor divider from V

shutdown levels with a 2.00V threshold at the UVLO pin.

Hysteresis is set by a switched internal 10uA current source that

forces additional current into the resistor divider.

5

UVLORTN Return for the external UVLO resistors, if

used.

Connect the bottom resistor of the resistor divider between the

UVLO pin and this pin.

6

RCLP

Current limit programming pin.

Programs the inrush current limit for the device. If left open, the

inrush current limit will default to 400mA max.

7V

EE

System low potential input.

Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is

the more negative input potential.

8

RTN

System return for the PWM converter.

The drain of the internal current limiting power MOSFET which

connects V

9

OUT

Output of the PWM controller.

DC-DC converter gate driver output with 800mA peak sink current

capability.

10

V

CC

Output of the internal high voltage series

pass regulator. Regulated output voltage

is nominally 7.8V.

When the auxiliary transformer winding (if used) raises the voltage

on this pin above the regulation set point, the internal series pass

regulator will shutdown, reducing the controller power dissipation.

11

FB

Feedback signal.

Inverting input of the internal error amplifier. The non-inverting

input is internally connected to a 1.25V reference.

12

COMP

The output of the error amplifier and

input to the Pulse Width Modulator.

COMP pull-up is provided by an internal 5K resistor which may be

used to bias an opto-coupler transistor.

13

CS

Current sense input.

Current sense input for current mode control and over-current

protection. Current limiting is accomplished using a dedicated

current sense comparator. If the CS pin voltage exceeds 0.5V the

OUT pin switches low for cycle-by-cycle current limiting. CS is held

low for 50ns after OUT switches high to blank leading edge current

spikes.

14

RT / SYNC Oscillator timing resistor pin and

synchronization input.

An external resistor connected from RT to ARTN sets the oscillator

frequency. This pin will also accept narrow ac-coupled

synchronization pulses from an external clock.

15

SS

Soft-start input.

An external capacitor and an internal 10uA current source set the

soft-start ramp rate.

16

ARTN

Analog PWM supply return.

RTN for sensitive analog circuitry including the SMPS current limit

amplifier.

—

EP

Exposed PAD, underside of the LLP

package option.

Internally bonded to the die substrate. Connect to V

low thermal impedance.

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